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Cpu Rtl Design Engineer Jobs in Rochester, NY (NOW HIRING)

University of Rochester

FPGA Design Engineer

Rochester, NY · On-site

$70.20K - $105.30K/yr

Requirements: - Strong working knowledge of VHDL coding - Experience with RTL simulation ... programming in Linux - CAD schematic capture The University of Rochester is committed to fostering ...

L3HHCM20

FPGA/ASIC Verification Engineer 1

Rochester, NY · Hybrid

$106.50K - $197.50K/yr

FPGA/ASIC RTL Design experience. * Proficiency in Object Oriented Programming(C++, JAVA). * Proven proficiency in FPGA/ASIC verification using SystemVerilog. * Working knowledge of UVM/OVM ...

Safran

Senior Software Engineer

Rochester, NY

$121.10K - $159.60K/yr

Experience with software architecture, open architecture, and software design * Experience with ... CPU cache behavior, concurrency, and network I/O optimization. * Experience working with digital ...

Safran

Senior Software Engineer

Rochester, NY · On-site

$80K - $135K/yr

Experience with software architecture, open architecture, and software design * Experience with ... CPU cache behavior, concurrency, and network I/O optimization. * Experience working with digital ...

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Cpu Rtl Design Engineer information

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$40K

$87K

$156.5K

How much do cpu rtl design engineer jobs pay per year?

As of May 28, 2026, the average yearly pay for cpu rtl design engineer in Rochester, NY is $87,014.00, according to ZipRecruiter salary data. Most workers in this role earn between $67,100.00 and $97,200.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a CPU RTL Design Engineer, and why are they important?

To thrive as a CPU RTL Design Engineer, you need a strong background in digital logic design, computer architecture, and proficiency in hardware description languages like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys or Cadence, and experience with simulation, synthesis, and verification methodologies are essential. Strong problem-solving skills, attention to detail, and effective teamwork are crucial soft skills for success in this role. These competencies enable the accurate implementation, debugging, and optimization of complex CPU designs, ensuring performance and reliability in final hardware products.

What are some common challenges faced by CPU RTL Design Engineers when collaborating with verification and architecture teams?

CPU RTL Design Engineers often work closely with both verification and architecture teams to ensure that the design meets functional and performance requirements. A common challenge is ensuring clear communication of design intent and handling feedback from verification regarding corner cases or bugs. Balancing architectural changes with design timelines and maintaining synchronization across multiple teams can be demanding. Successful engineers proactively document their work, participate in regular sync-ups, and are open to iterative improvements based on collaborative feedback.

What are CPU RTL Design Engineers?

CPU RTL (Register Transfer Level) Design Engineers are specialized hardware engineers who design, implement, and verify the digital logic that forms the core of computer processors. They use hardware description languages like Verilog or VHDL to create and simulate the functional blocks of CPUs, ensuring correct operation and optimal performance. Their work involves close collaboration with architecture, verification, and physical design teams to bring processor designs from conception to silicon. They also debug and optimize designs to meet power, speed, and area goals.

What is the difference between Cpu Rtl Design Engineer vs Cpu Verification Engineer?

AspectCpu Rtl Design EngineerCpu Verification Engineer
Primary FocusDesigning and developing RTL code for CPU componentsVerifying and testing RTL designs for correctness
Skills & CertificationsHDL languages (Verilog/VHDL), FPGA/ASIC design experienceHDL, testbench development, simulation tools
Work EnvironmentDesign teams, hardware development labsVerification teams, simulation environments
Industry UsageSemiconductor companies, CPU design firmsASIC/FPGA verification, chip validation

While both roles require HDL knowledge and work within hardware design environments, Cpu Rtl Design Engineers focus on creating the RTL code for CPU components, whereas Cpu Verification Engineers concentrate on testing and validating those designs to ensure functionality and performance.

What are popular job titles related to Cpu Rtl Design Engineer jobs in Rochester, NY? For Cpu Rtl Design Engineer jobs in Rochester, NY, the most frequently searched job titles are:
What job categories do people searching Cpu Rtl Design Engineer jobs in Rochester, NY look for? The top searched job categories for Cpu Rtl Design Engineer jobs in Rochester, NY are:
What cities near Rochester, NY are hiring for Cpu Rtl Design Engineer jobs? Cities near Rochester, NY with the most Cpu Rtl Design Engineer job openings:
Cpu Rtl Design Engineer jobs near you
Infographic showing various Cpu Rtl Design Engineer job openings in Rochester, NY as of May 2026, with employment types broken down into 1% As Needed, 8% Full Time, 61% Part Time, and 30% Contract. Highlights an 95% Physical, and 5% Remote job distribution, with an average salary of $87,014 per year, or $41.8 per hour.
FPGA Design Engineer

FPGA Design Engineer

University of Rochester

Rochester, NY

$70.20K - $105.30K/yr

Full-time

Posted yesterday

University Of Rochester rating

8.3

Company rating: 8.3 out of 10

Based on 178 frontline employees who took The Breakroom Quiz

92nd of 528 rated colleges and universities

Job description

As a community, the University of Rochester is defined by a deep commitment to Meliora - Ever Better. Embedded in that ideal are the values we share: equity, leadership, integrity, openness, respect, and accountability. Together, we will set the highest standards for how we treat each other to ensure our community is welcoming to all and is a place where all can thrive.

Job Location (Full Address):

250 East River Rd, Rochester, New York, United States of America, 14623

Opening:

Worker Subtype:

Regular

Time Type:

Full time

Scheduled Weekly Hours:

40

Department:

250548 LLE-Laboratory for Laser Energ

Work Shift:

UR - Day (United States of America)

Range:

UR URG 112

Compensation Range:

$70,197.00 - $105,295.00

The referenced pay range represents the minimum and maximum compensation for this job. Individual annual salaries/hourly rates will be set within the job's compensation range, and will be determined by considering factors including, but not limited to, market data, education, experience, qualifications, expertise of the individual, and internal equity considerations.

Responsibilities:

The Laboratory for Laser Energetics (LLE) of the University of Rochester is a unique national resource for research and education in science and technology focusing on using lasers to initiate fusion and high energy density physics.
The LLE Electronics and Controls Engineering group has a broad portfolio of custom embedded electronics and consumer off the shelf (COTS) products deployed across the lab. We are seeking an experienced FPGA design engineer to aid in the development of new solutions and support of the exiting install base of devices across the facility. The successful candidate should have a BSEE/BSEET and 3 years of experience or equivalent training and experience.

Requirements:


- Strong working knowledge of VHDL coding
- Experience with RTL simulation
- Familiarity with circuit design, development, and troubleshooting
Desired skills or experience includes:
- Experience with AMD/Xilinx Vivado or ISE
- Familiarity with high-speed transceivers used in PCIe or fiber optics
- Embedded programming in Linux
- CAD schematic capture

The University of Rochester is committed to fostering, cultivating, and preserving an inclusive and welcoming culture to advance the University's Mission to Learn, Discover, Heal, Create - and Make the World Ever Better. In support of our values and those of our society, the University is committed to not discriminating on the basis of age, color, disability, ethnicity, gender identity or expression, genetic information, marital status, military/veteran status, national origin, race, religion, creed, sex, sexual orientation, citizenship status,or any other characteristic protected by federal, state, or local law (Protected Characteristics). This commitment extends to non-discrimination in the administration of our policies, admissions, employment, access, and recruitment of candidates, for all persons consistent with our values and based on applicable law.

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