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Cpu Rtl Design Engineer Jobs in Rochester, NY (NOW HIRING)

Fermilab

FPGA Firmware Developer

Batavia, NY · On-site

$99K - $130K/yr

Fermilab is seeking a FPGA Firmware Developer who will design, develop, verify, and integrate FPGA-based systems and embedded firmware. Responsibilities include architecture definition, RTL ...

Amat

FPGA Engineer IV

Rochester, NY

$156K - $214K/yr

Design, implementation, and test of complex FPGA's used with system on chip and heterogenous ... RTL and VHDL experience; High Level Synthesis experience desired. * Skilled in TCL and Python ...

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Cpu Rtl Design Engineer information

See Rochester, NY salary details

$40K

$87.1K

$156.6K

How much do cpu rtl design engineer jobs pay per year?

As of Sep 11, 2026, the average yearly pay for cpu rtl design engineer in Rochester, NY is $87,108.00, according to ZipRecruiter salary data. Most workers in this role earn between $67,200.00 and $97,300.00 per year, depending on experience, location, and employer.

What is a CPU RTL design engineer?

CPU RTL (Register Transfer Level) Design Engineers are specialized hardware engineers who design, implement, and verify the digital logic that forms the core of computer processors. They use hardware description languages like Verilog or VHDL to create and simulate the functional blocks of CPUs, ensuring correct operation and optimal performance. Their work involves close collaboration with architecture, verification, and physical design teams to bring processor designs from conception to silicon. They also debug and optimize designs to meet power, speed, and area goals.

What are the key skills and qualifications needed to thrive as a CPU RTL design engineer?

To thrive as a CPU RTL Design Engineer, you need a strong background in digital logic design, computer architecture, and proficiency in hardware description languages like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys or Cadence, and experience with simulation, synthesis, and verification methodologies are essential. Strong problem-solving skills, attention to detail, and effective teamwork are crucial soft skills for success in this role. These competencies enable the accurate implementation, debugging, and optimization of complex CPU designs, ensuring performance and reliability in final hardware products.

What are some common challenges faced by CPU RTL design engineers when collaborating with verification and architecture teams?

CPU RTL Design Engineers often work closely with both verification and architecture teams to ensure that the design meets functional and performance requirements. A common challenge is ensuring clear communication of design intent and handling feedback from verification regarding corner cases or bugs. Balancing architectural changes with design timelines and maintaining synchronization across multiple teams can be demanding. Successful engineers proactively document their work, participate in regular sync-ups, and are open to iterative improvements based on collaborative feedback.

What is the difference between Cpu Rtl Design Engineer vs Cpu Verification Engineer?

AspectCpu Rtl Design EngineerCpu Verification Engineer
Primary FocusDesigning and developing RTL code for CPU componentsVerifying and testing RTL designs for correctness
Skills & CertificationsHDL languages (Verilog/VHDL), FPGA/ASIC design experienceHDL, testbench development, simulation tools
Work EnvironmentDesign teams, hardware development labsVerification teams, simulation environments
Industry UsageSemiconductor companies, CPU design firmsASIC/FPGA verification, chip validation

While both roles require HDL knowledge and work within hardware design environments, Cpu Rtl Design Engineers focus on creating the RTL code for CPU components, whereas Cpu Verification Engineers concentrate on testing and validating those designs to ensure functionality and performance.

What are popular job titles related to Cpu Rtl Design Engineer jobs in Rochester, NY?

For Cpu Rtl Design Engineer jobs in Rochester, NY, the most frequently searched job titles are:

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The top searched job categories for Cpu Rtl Design Engineer jobs in Rochester, NY are:

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Cities near Rochester, NY with the most Cpu Rtl Design Engineer job openings:

Cpu Rtl Design Engineer jobs near you
Infographic showing various Cpu Rtl Design Engineer job openings in Rochester, NY as of August 2026, with employment types broken down into 82% Full Time, 12% Part Time, and 6% Contract. Highlights an 81% Physical, 5% Hybrid, and 14% Remote job distribution, with an average salary of $87,014 per year, or $41.8 per hour.

RTL Design Engineer

Rochester, NY • On-site

Advanced Micro Devices, Inc
Computer and Electronic Product Manufacturing • 5 - 10K employees
Learn more about Advanced Micro Devices, Incexternal

$126K/yr

Full-time

Posted 25 days ago

Key responsibilities

  • Own top-level RTL design and analog macro integration for mixed-signal power management IC

  • Drive timing closure and ECO support through tape-out, including creating and reviewing timing constraints and managing tradeoffs

  • Partner with verification, analog, firmware, and physical design teams to validate models, debug failures, and support post-silicon bring-up

Advanced Micro Devices rating

8.6

Company rating: 8.6 out of 10

Based on 13 frontline employees who took The Breakroom Quiz

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.
At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we're looking for talent who feel the same: people who want to leave the planet better than they found it, those who don't shy away from humanity's challenges but are determined to help solve them.
AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you're designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger - technology that moves the world forward.
THE ROLE:
The focus of this role is to own the top-level RTL design and integration of AMD's mixed-signal power management IP, and to drive that design through timing closure and tape-out in partnership with our physical design and verification teams.
THE PERSON:
You have a passion for digital design, mixed-signal integration, and silicon that works for the first time. You are a team player with excellent communication skills and experience collaborating with design, analog, firmware, and physical design teams. You have strong analytical and problem-solving skills, and you are ready to take ownership of hard problems.
KEY RESPONSIBILITIES:
Top-Level SOC Design
  • Own top-level RTL design and analog macro integration for mixed-signal power management IC
  • Partner with analog macro teams on block integration, including bring-up and debug of analog behavioral models in the digital simulation environment
  • Author micro-architecture specifications in partnership with Architecture and Firmware

Physical Design, Timing & Design Quality
  • Act as primary interface between RTL design and the Physical Design / timing closure team
  • Create and review timing constraints (SDC), including analog macro boundaries and clock-domain crossings
  • Drive timing closure and ECO support through tape-out; manage area, power, and floorplan tradeoffs with PD
  • Own RTL signoff before each release to PD: lint, CDC/RDC, synthesis QoR, and connectivity checks

Verification & Bring-Up
  • Partner with the verification team to define and review test plans and coverage goals
  • Validate analog behavioral models against analog design intent for functionality and timing, and drive discrepancies to resolution with the Analog team
  • Debug block- and system-level simulation failures to root cause
  • Support post-silicon bring-up and silicon-to-RTL correlation

Collaboration
  • Work across Analog, Firmware, Systems Engineering, and Architecture teams
  • Mentor junior engineers and lead design reviews

PREFERRED EXPERIENCE
  • RTL design in SystemVerilog, with ownership of blocks or subsystems through tape-out
  • Hands-on experience with timing constraints (SDC) development and timing closure on production silicon
  • Proficiency with synthesis, lint, and CDC/RDC tools and their integration into a design flow
  • Strong scripting skills in Python and TCL
  • Top-level SOC or chip-level integration ownership on a mixed-signal device
  • Integration and debug of analog behavioral models (Verilog-AMS, real-number/wreal modeling) in a digital simulation environment
  • Low-power design methodology and UPF-based power intent
  • Familiarity with standard control interfaces used in power management (I²C, SPI, APB, SVID/PMBus)
  • Post-silicon bring-up and debug experience, including silicon-to-RTL correlation

ACADEMIC CREDENTIALS:
  • Bachelors or master's in electrical/computer engineering

This role is not eligible for visa sponsorship.
#LI-DP1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here.
This posting is for an existing vacancy.

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