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Junior Rtl Design Engineer Jobs in New York (NOW HIRING)

Normal Computing

Hardware Engineer, RTL

New York, NY · On-site

$200K - $285K/yr

We co-design the full stack: AI-native EDA systems in production with the world's largest ... The Role As an RTL Design Engineer at Normal, you will design and verify the digital logic at the ...

Normal Computing

Hardware Engineer, RTL/PD

New York, NY · On-site

$200K - $285K/yr

We co-design the full stack: AI-native EDA systems in production with the world's largest ... The Role As an RTL and PD Design Engineer at Normal, you will take and optimize RTL through ...

New

Quantum Computing Inc.

FPGA Design Engineer

Hoboken, NJ · On-site

$134K - $185K/yr

FPGA Design Engineer Location: Hoboken, NJ Division : Technology Department: Engineering Reports to ... Develop RTL code for use within multiple projects. Analyze and enhance efficiency, scalability, and ...

QCi

FPGA Design Engineer

Hoboken, NJ · On-site

$134K - $185K/yr

FPGA Design Engineer Location: Hoboken, NJ Division : Technology Department: Engineering Reports to ... Develop RTL code for use within multiple projects. Analyze and enhance efficiency, scalability, and ...

Cloud Peritus

Hardware Engineer

New York, NY · On-site

$135K - $178K/yr

We are looking for a hardware engineer to join our high frequency trading technology team ... Responsibilities: • Architect and implement FPGA applications (RTL design, synthesis, place ...

Jane Street

ASIC Physical Design Engineer

New York, NY · On-site

$148K - $153K/yr

You should be comfortable owning a PD flow end-to-end, but also able to read and write RTL and ... using software engineering techniques to improve the hardware design process, and you have ...

Cloud Peritus

Hardware Engineer

New York, NY · On-site

$135K - $178K/yr

We are looking for a hardware engineer to join our high frequency trading technology team ... Architect and implement FPGA applications (RTL design, synthesis, place & route, timing closure)

Jane Street

ASIC Physical Design Engineer

New York, NY

$148K - $153K/yr

You should be comfortable owning a PD flow end-to-end, but also able to read and write RTL and ... using software engineering techniques to improve the hardware design process, and you have ...

Jane Street

ASIC Engineer

New York, NY · On-site

$181K/yr

Have 4+ years practical experience in RTL design and verification * Experienced in ASIC design ... Interested in using software engineering techniques to improve the hardware design process, and ...

Jane Street

ASIC Engineer

New York, NY

$181K/yr

Have 4+ years practical experience in RTL design and verification * Experienced in ASIC design ... Interested in using software engineering techniques to improve the hardware design process, and ...

Airspan

FPGA DESIGN ENGINEER

Warren, NJ · On-site

$127K - $176K/yr

Airspan Careers FPGA DESIGN ENGINEER Location: Warren, New Jersey or Plano, TX, Remote possible if ... Develop RTL designs in Verilog/System Verilog , ensuring efficient and high-performance ...

Ashby

Design Engineer - Americas

New York, NY · Remote

$126K - $250K/yr

Junior Design Engineer - You should have no more than 2 years of industry experience as a designer or engineer. We want to see projects (personal or professional) with at least a couple of users that ...

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Junior Rtl Design Engineer information

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$36.6K

$78.6K

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How much do junior rtl design engineer jobs pay per year?

As of Aug 4, 2026, the average yearly pay for junior rtl design engineer in New York is $78,551.00, according to ZipRecruiter salary data. Most workers in this role earn between $53,100.00 and $87,500.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a junior RTL design engineer?

To thrive as a Junior RTL Design Engineer, a solid background in digital logic design, hardware description languages (such as Verilog or VHDL), and a relevant engineering degree are essential. Experience with simulation and synthesis tools (like ModelSim, Synopsys, or Xilinx Vivado) and a basic understanding of ASIC or FPGA flows are typically required. Strong analytical thinking, attention to detail, and effective teamwork skills help individuals excel in translating specifications into efficient hardware designs. These skills ensure accurate, reliable, and high-performance digital circuit development, which is crucial for meeting project goals and industry standards.

What is a junior RTL design engineer?

Junior RTL Design Engineers are entry-level professionals who work on designing and verifying the Register Transfer Level (RTL) logic for digital integrated circuits. They typically use hardware description languages like Verilog or VHDL to describe and simulate the functionality of hardware blocks according to specifications. Their responsibilities often include coding, simulation, debugging, and collaborating with senior engineers to ensure the design meets performance and functional requirements. This role is crucial in the process of creating chips and digital systems used in various electronic devices.

What is the difference between Junior Rtl Design Engineer vs Digital Design Engineer?

AspectJunior Rtl Design EngineerDigital Design Engineer
Required CredentialsBachelor's in Electrical Engineering or related field; some certificationsBachelor's or higher in Electrical/Electronic Engineering; certifications vary
Work EnvironmentDesign teams in semiconductor or electronics companiesDesign and development teams in similar industries
Employer & Industry UsageCommonly employed in chip design, FPGA, ASIC developmentUsed in digital circuit and system design across industries

Both roles involve digital circuit design, but Junior Rtl Design Engineers focus more on RTL coding and verification, while Digital Design Engineers may handle broader digital system development. The roles often overlap in skills and work environment, with the main difference being scope and experience level.

What are some common challenges faced by junior RTL design engineers when transitioning from academic projects to industry roles?

Junior RTL Design Engineers often find the transition from academic projects to industry roles challenging due to the increased complexity and scale of commercial designs. In industry, there is a strong emphasis on meeting strict timing, power, and area requirements, as well as adhering to rigorous verification and documentation standards. Collaboration with verification, physical design, and software teams is essential, and juniors may need to quickly adapt to using industry-standard EDA tools and workflows. Gaining proficiency in debugging and understanding legacy codebases are also typical hurdles. However, most teams provide mentorship and structured onboarding to help new engineers succeed.
What are popular job titles related to Junior Rtl Design Engineer jobs in New York? For Junior Rtl Design Engineer jobs in New York, the most frequently searched job titles are:
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Junior Rtl Design Engineer jobs near you

Hardware Engineer, RTL

Normal Computing

New York, NY • On-site

$200K - $285K/yr

Full-time

Re-posted yesterday

Job description

About Normal Computing
Normal Computing builds silicon that turns thermal noise from an obstacle into a computational resource. Conventional chips spend most of their energy forcing determinism onto physics; ours compute with it. Stochastic, in-memory, asynchronous: the result is 10-100× more AI inference per dollar, per watt.
We co-design the full stack: AI-native EDA systems in production with the world's largest semiconductor companies, and the advanced ASICs they make possible. Backed by $85M+ from the world's leading deep-tech investors and built by scientists, engineers, and operators from the labs that built modern computing.
Normal works as one team across New York, Silicon Valley, London, Copenhagen, and Seoul. We hire people who want the hardest version of their craft, across every discipline, at every seniority.
The Role
As an RTL Design Engineer at Normal, you will design and verify the digital logic at the heart of Normal's thermodynamic hardware. This work sits at the intersection of classical ASIC design, novel computing architectures, and a development environment where the hardware and the algorithms are built together, not in sequence.
You will own RTL from microarchitecture to tapeout: writing microarchitecture specifications, creating synthesizable SystemVerilog, working with design verification engineers fully test the design using conventional and formal methods, and working closely physical design to make sure the design meets area and timing constraints. Because Normal's chips are not standard accelerators, the RTL engineer here is closer to first-principles decisions than at a larger company. You will be shaping architecture, not just implementing it.
This is a role for an engineer who collaborates effectively across teams, including architecture, verification and physical design. The strongest candidates have taped out silicon, written RTL and helped close coverage, and are comfortable working in an environment where the specification is still being developed in parallel.
What You'll Own
  • RTL Design: Write and own synthesizable RTL in SystemVerilog across blocks ranging from datapath logic to control and memory interfaces.
  • Microarchitecture: Work with architecture to translate high-level specifications into implementable microarchitectures.
  • Verification: Work closely with the verification team to review verification plans, assist on debug, and become a partner in closing coverage.
  • Physical Design Collaboration: Collaborate with physical design on timing closure, floorplanning constraints, and DFT.
  • Design Reviews: Participate in design reviews and contribute to architecture decisions, not just implementation.
  • Tapeout & Bring-up: Support tapeout preparation, integration, and post-silicon bring-up as needed.

What Makes You a Great Fit
  • Hands-on experience writing production RTL in SystemVerilog and closing it through synthesis and place-and-route
  • Experience in closing coverage to a high level
  • At least one tapeout in your background, from any node and any company size
  • Experience working on datapaths, pipelines, or custom logic where the microarchitecture was not fully specified upfront
  • Strong debugging instincts across simulation, waveforms, and formal counterexamples
  • Ability to work directly with architects and physical designers without needing a large intermediary layer
  • Industry experience in ASIC or SoC design

Bonus Points
  • Experience at an AI chip company where design and verification were tightly coupled
  • Open-source RTL contributions to projects like Chipyard, OpenTitan, or CVA6
  • Familiarity with RISC-V or other open ISAs
  • Experience with AI-assisted RTL or EDA tooling in your design workflow
  • Exposure to physical design constraints, floorplanning, or timing-driven RTL development

Equal Employment Opportunity Statement
Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.
Accessibility Accommodations
Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at accommodations@normalcomputing.com.
Privacy Notice
By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Privacy Policy.

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