Hillsboro, OR · On-site
$106K - $198K/yr
RTL coding and verification * Memory Controller + PHY integration and verification * Customer ... Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently
Hillsboro, OR · On-site
$106K - $198K/yr
RTL coding and verification * Memory Controller + PHY integration and verification * Customer ... Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently
$147K - $272K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
$147K - $272K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
$126K - $190K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
$126K - $190K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
$126K - $190K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
$126K - $190K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
$147K - $272K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
$147K - $272K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
Beaverton, OR · On-site
$121K - $174K/yr
... RTL, Standard cells, and similar approaches as necessary for both mixed signal ASIC and FPGA ... Digital Design Engineer or related occupation performing digital or mixed signal design and ...
Beaverton, OR · On-site
$121K - $174K/yr
... RTL, Standard cells, and similar approaches as necessary for both mixed signal ASIC and FPGA ... Digital Design Engineer or related occupation performing digital or mixed signal design and ...
Beaverton, OR · On-site
$121K - $174K/yr
... RTL, Standard cells, and similar approaches as necessary for both mixed signal ASIC and FPGA ... Digital Design Engineer or related occupation performing digital or mixed signal design and ...
Beaverton, OR · On-site
$121K - $174K/yr
... RTL, Standard cells, and similar approaches as necessary for both mixed signal ASIC and FPGA ... Digital Design Engineer or related occupation performing digital or mixed signal design and ...
RTL coding: Verilog / System Verilog * Master's degree or PHD in Electrical Engineering, Computer Engineering or equivalent. * 5+ years of experience with RTL Design * Good English skills ...
RTL coding: Verilog / System Verilog * Master's degree or PHD in Electrical Engineering, Computer Engineering or equivalent. * 5+ years of experience with RTL Design * Good English skills ...
RTL coding: Verilog / System Verilog * Master's degree or PHD in Electrical Engineering, Computer Engineering or equivalent. * 7+ years of experience with RTL Design * Good English skills ...
RTL coding: Verilog / System Verilog * Master's degree or PHD in Electrical Engineering, Computer Engineering or equivalent. * 7+ years of experience with RTL Design * Good English skills ...
Hillsboro, OR · On-site
$141K - $200K/yr
Key Responsibilities - Develop high-quality logic designs, including Register Transfer Level (RTL ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...
Hillsboro, OR · On-site
$141K - $200K/yr
Key Responsibilities - Develop high-quality logic designs, including Register Transfer Level (RTL ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...
Hillsboro, OR · On-site
$141K - $200K/yr
Key Responsibilities - Develop high-quality logic designs, including Register Transfer Level (RTL ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...
Hillsboro, OR · On-site
$141K - $200K/yr
Key Responsibilities - Develop high-quality logic designs, including Register Transfer Level (RTL ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...
We are now looking for a Senior Logic Design Engineer! As a member of our CPU Logic Design Team ... Verilog expertise required as is a deep understanding of ASIC design flow including RTL design ...
We are now looking for a Senior Logic Design Engineer! As a member of our CPU Logic Design Team ... Verilog expertise required as is a deep understanding of ASIC design flow including RTL design ...
$200K - $280K/yr
The Role We are seeking a Principal ASIC Package Design Engineer to lead advanced ASIC package architecture and execution, with a strong focus on flip-chip BGA (FC-BGA) and multi-chip module (MCM ...
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
Beaverton, OR · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
Beaverton, OR · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
$180K - $260K/yr
The Role We are seeking a Senior ASIC Package Design Engineer to implement advanced ASIC package architecture, with a strong focus on flip-chip BGA (FC-BGA) and multi-chip module (MCM) solutions.
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
Beaverton, OR · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
Beaverton, OR · On-site
Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC ... You will closely interact with RTL designer to understand design intent and clock structure, with ...
... design to target power, performance, area and timing goals • Verification - support the ... RTL design meets targeted performance • Design delivery - work with multi-functional engineering ...
... design to target power, performance, area and timing goals • Verification - support the ... RTL design meets targeted performance • Design delivery - work with multi-functional engineering ...
... design to target power, performance, area and timing goals • Verification - support the ... RTL design meets targeted performance • Design delivery - work with multi-functional engineering ...
... design to target power, performance, area and timing goals • Verification - support the ... RTL design meets targeted performance • Design delivery - work with multi-functional engineering ...
| Aspect | Contractual Asic Rtl Design Engineer | Digital IC Design Engineer |
|---|---|---|
| Credentials | Bachelor's/Master's in Electrical Engineering or Computer Engineering | Bachelor's/Master's in Electrical Engineering or Computer Engineering |
| Work Environment | Contract-based, project-specific, often in semiconductor or tech companies | Full-time or contract, working on digital integrated circuit design |
| Industry Usage | Common in semiconductor, electronics, and tech firms for ASIC development | Used across semiconductor, consumer electronics, and communication industries |
Both roles require similar educational backgrounds and work in related environments, focusing on digital circuit design. The main difference is that Contractual Asic Rtl Design Engineers typically work on specific ASIC projects on a contractual basis, while Digital IC Design Engineers may have broader responsibilities in digital chip development, often in full-time roles.
$106K - $198K/yr
Other
Medical, Dental, Retirement
Posted 6 days ago
Sourced by ZipRecruiter
Semiconductor and electronic component manufacturing
501 - 1,000 Employees
Sunnyvale, CA, US
1990
