Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design ... Verilog RTL Logic Design experience.
Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design ... Verilog RTL Logic Design experience.
Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design ... Verilog RTL Logic Design experience.
Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design ... Verilog RTL Logic Design experience.
ASIC Design Engineer
Beaverton, OR · On-site
Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design ... Verilog RTL Logic Design experience. Preferred Qualifications Experience writing specifications and ...
ASIC Design Engineer
Beaverton, OR · On-site
Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design ... Verilog RTL Logic Design experience. Preferred Qualifications Experience writing specifications and ...
RTL design and implementation for ASIC/SoC development * Proficiency in Verilog/System Verilog for ... programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting ...
RTL design and implementation for ASIC/SoC development * Proficiency in Verilog/System Verilog for ... programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting ...
As a CPU RTL Logic Design Engineer your responsibilities will include but are not limited to: Collaborates, drives and develops logic design, register transfer level (RTL) coding, and simulation for ...
As a CPU RTL Logic Design Engineer your responsibilities will include but are not limited to: Collaborates, drives and develops logic design, register transfer level (RTL) coding, and simulation for ...
FE RTL Infrastructure - CAD Engineer
Beaverton, OR · On-site
$172K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
FE RTL Infrastructure - CAD Engineer
Beaverton, OR · On-site
$172K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
FE RTL Infrastructure - CAD Engineer
Beaverton, OR · On-site
$172K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
FE RTL Infrastructure - CAD Engineer
Beaverton, OR · On-site
$172K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
Principal Logic Design Engineer
Hillsboro, OR · On-site
$127K - $236K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Principal Logic Design Engineer
Hillsboro, OR · On-site
$127K - $236K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $236K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $236K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $236K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $236K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Principal Logic Design Engineer
Hillsboro, OR · On-site
$127K - $236K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Principal Logic Design Engineer
Hillsboro, OR · On-site
$127K - $236K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $236K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $236K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $236K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $236K/yr
Own micro-architecture definition and RTL design for critical blocks such as schedulers, command ... ASIC synthesis, timing constraint, CDC/RDC experience * UVM Verification experience * Memory (HBM ...
$170K - $250K/yr
The Role We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that ... RTL, verification, and packaging teams. You'll be a key contributor in achieving timing closure ...
DDR Design Engineer
Beaverton, OR · On-site
As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...
DDR Design Engineer
Beaverton, OR · On-site
As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...
Hardware Design Engineer
Hillsboro, OR · Hybrid
$106K - $198K/yr
RTL coding and verification * Memory Controller + PHY integration and verification * Customer ... Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently
Hardware Design Engineer
Hillsboro, OR · Hybrid
$106K - $198K/yr
RTL coding and verification * Memory Controller + PHY integration and verification * Customer ... Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently
Hardware Design Engineer
Hillsboro, OR · Hybrid
$106K - $198K/yr
RTL coding and verification * Memory Controller + PHY integration and verification * Customer ... Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently
Hardware Design Engineer
Hillsboro, OR · Hybrid
$106K - $198K/yr
RTL coding and verification * Memory Controller + PHY integration and verification * Customer ... Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently
DDR Design Engineer
Beaverton, OR · On-site
As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...
DDR Design Engineer
Beaverton, OR · On-site
As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...
As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...
As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...
As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...
As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...
Contractual Asic Rtl Design Engineer information
What is the difference between Contractual Asic Rtl Design Engineer vs Digital IC Design Engineer?
| Aspect | Contractual Asic Rtl Design Engineer | Digital IC Design Engineer |
|---|---|---|
| Credentials | Bachelor's/Master's in Electrical Engineering or Computer Engineering | Bachelor's/Master's in Electrical Engineering or Computer Engineering |
| Work Environment | Contract-based, project-specific, often in semiconductor or tech companies | Full-time or contract, working on digital integrated circuit design |
| Industry Usage | Common in semiconductor, electronics, and tech firms for ASIC development | Used across semiconductor, consumer electronics, and communication industries |
Both roles require similar educational backgrounds and work in related environments, focusing on digital circuit design. The main difference is that Contractual Asic Rtl Design Engineers typically work on specific ASIC projects on a contractual basis, while Digital IC Design Engineers may have broader responsibilities in digital chip development, often in full-time roles.
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Apple rating
8.1
Based on 662 frontline employees who took The Breakroom Quiz
6th of 30 rated technology retailers
Job description
Imagine what you could do here. At Apple, new insights have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Sophisticated, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it. Join us to help deliver the next excellent Apple product. Do you enjoy working on challenges that no one has solved yet? As a member of our complex group, you will get the outstanding and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every single day. Are you ready to join a team transforming hardware technology? We are searching for a dedicated engineer to join our exciting team of problem solvers.
Description
As an ASIC Design Engineer, your responsibilities span various aspects of SOC design:
- Write microarchitecture and/or design specifications
- Design, implement, and debug complex logic designs
- Integrate complex IPs into the SOC
- Support all front end integration activities like Lint, CDC, Synthesis, and ECO
- Work with other specialists that are members of the SOC Design, SOC Design
- Verification, Emulation, STA, and Physical Design teams
- Collaborate with software and systems teams to ensure a high quality
Preferred Qualifications
Experience writing specifications and converting them to design.
Experience with multiple clock domains and asynchronous interfaces.
Hands on experience in all aspects of the chip development process with proficiency in front end tools and methodologies
Experience or knowledge of system architecture, CPU & IP Integration, and power and clock management designs desirable.
Ability to communicate optimally across all internal groups
Familiarity with software and operating concepts a plus
Familiarity with scripting languages like Perl, Python, or TCL a plus
Minimum Qualifications
BS and a minimum of 3 years relevant industry experience.
Verilog RTL Logic Design experience.
Description
As an ASIC Design Engineer, your responsibilities span various aspects of SOC design:
- Write microarchitecture and/or design specifications
- Design, implement, and debug complex logic designs
- Integrate complex IPs into the SOC
- Support all front end integration activities like Lint, CDC, Synthesis, and ECO
- Work with other specialists that are members of the SOC Design, SOC Design
- Verification, Emulation, STA, and Physical Design teams
- Collaborate with software and systems teams to ensure a high quality
Preferred Qualifications
Experience writing specifications and converting them to design.
Experience with multiple clock domains and asynchronous interfaces.
Hands on experience in all aspects of the chip development process with proficiency in front end tools and methodologies
Experience or knowledge of system architecture, CPU & IP Integration, and power and clock management designs desirable.
Ability to communicate optimally across all internal groups
Familiarity with software and operating concepts a plus
Familiarity with scripting languages like Perl, Python, or TCL a plus
Minimum Qualifications
BS and a minimum of 3 years relevant industry experience.
Verilog RTL Logic Design experience.
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976