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Eridu AI

ASIC Chip Design Lead

Saratoga, CA · On-site

$250K - $280K/yr

Position Overview We are seeking a hands-on ASIC Chip Design Lead to own chip design execution from micro-architecture through full-chip integration and timing signoff. This role sits between senior ...

Conductor

NoC Architect (Network on Chip)

San Francisco, CA · On-site

$76.25 - $102.25/hr

We're looking for an architect to own the NoC (network on chip) inside our XPU, as well as its integration into the broader network and system. Ideal Background: * Hands on experience in designing ...

NXP Semiconductors

Chip Lead

Austin, TX · Hybrid

$101K - $133K/yr

AI & Chip Engineering team defines and develops System on Chip, ASIC's, Digital and Analog IP'sfor a wide range of products, including Automotive microprocessors, Application processors, Data Center ...

Conductor

NoC Architect (Network on Chip)

Boston, MA · On-site

$70.25 - $94.25/hr

We're looking for an architect to own the NoC (network on chip) inside our XPU, as well as its integration into the broader network and system. Ideal Background: * Hands on experience in designing ...

VSS International, Inc.

Chip Seal Laborer

Chandler, AZ · On-site

$16.25 - $20/hr

Chip Seal Laborer assists in preparing streets for chip seal, slurry seals on roads and streets. The Laborer assists with the repair and maintenance of the City streets and right of ways by ...

NXP Semiconductors N.V.

Chip Lead

Austin, TX · On-site

$101K - $133K/yr

AI & Chip Engineering team defines and develops System on Chip, ASIC's, Digital and Analog IP's for a wide range of products, including Automotive microprocessors, Application processors, Data Center ...

Lattice Semiconductor

SoC Chip Lead

San Jose, CA

We are seeking a SoC Chip Lead with deep technical expertise and a track record of delivering complex silicon from concept to production. You will architect and implement high-quality IP across ...

VSS International, Inc.

Chip Seal Laborer

Chandler, AZ · On-site

$15.75 - $19.75/hr

Chip Seal Laborer assists in preparing streets for chip seal, slurry seals on roads and streets. The Laborer assists with the repair and maintenance of the City streets and right of ways by ...

VSS International, Inc.

Chip Seal Laborer

Chandler, AZ

$16 - $19.75/hr

Chip Seal Laborer assists in preparing streets for chip seal, slurry seals on roads and streets. The Laborer assists with the repair and maintenance of the City streets and right of ways by ...

Lattice Semiconductor

SoC Chip Lead

San Jose, CA · On-site

We are seeking a SoC Chip Lead with deep technical expertise and a track record of delivering complex silicon from concept to production. You will architect and implement high-quality IP across ...

Conductor

NoC Architect (Network on Chip)

Austin, TX · On-site

$64.25 - $86/hr

We're looking for an architect to own the NoC (network on chip) inside our XPU, as well as its integration into the broader network and system. Ideal Background: * Hands on experience in designing ...

VSS International, Inc.

Chip Seal Laborer

Chandler, AZ · On-site

$15.75 - $19.75/hr

Chip Seal Laborer assists in preparing streets for chip seal, slurry seals on roads and streets. The Laborer assists with the repair and maintenance of the City streets and right of ways by ...

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Chip information

What does a chip engineer do?

Chip engineers, also known as semiconductor or integrated circuit (IC) engineers, design, develop, and test microchips or semiconductor devices used in electronic equipment. They work on the architecture, layout, and manufacturing processes for chips that power everything from smartphones to computers and cars. Their responsibilities include circuit design, simulation, verification, and ensuring chips meet performance and reliability standards. Chip engineers often collaborate with software engineers and hardware teams to integrate chips into larger systems. Their work is crucial to advancing technology in many industries.

What are some of the typical challenges faced by chip design engineers during the development cycle?

Chip design engineers often encounter challenges such as meeting tight performance and power consumption targets, ensuring design verification coverage, and managing complex cross-functional collaboration with software, hardware, and testing teams. Balancing optimal design with manufacturability and cost constraints is also a common concern. Staying updated on rapidly evolving semiconductor technologies and adhering to industry standards requires continual learning and adaptability.

What are the key skills and qualifications needed to thrive as a chip design engineer, and why are they important?

To thrive as a Chip Design Engineer, you need a strong background in electrical engineering, digital logic design, and semiconductor physics, usually supported by a relevant degree. Proficiency with hardware description languages (HDLs) like VHDL or Verilog, and experience using industry-standard EDA tools such as Cadence or Synopsys, are typically required. Analytical thinking, attention to detail, and effective teamwork are vital soft skills for excelling in this field. These skills ensure innovative, efficient, and error-free chip designs that meet rigorous industry standards.

What is the difference between Chip vs PCB Designer?

AspectChipPCB Designer
Required CredentialsElectrical Engineering degree, VLSI/ASIC design certificationsElectrical Engineering or related degree, PCB design certifications (e.g., IPC)
Work EnvironmentSemiconductor fabrication labs, R&D centersElectronics manufacturing, engineering offices
Industry UsageSemiconductor industry, integrated circuit manufacturingConsumer electronics, industrial equipment
Common Search/ComparisonChip design, VLSI, ASICPCB layout, circuit board design

In summary, a Chip focuses on designing integrated circuits at the silicon level, requiring specialized knowledge in VLSI and semiconductor fabrication. A PCB Designer, on the other hand, creates the physical layout of circuit boards used in electronic devices. Both roles are essential in electronics but differ significantly in scope, environment, and technical expertise.

How to become a chip worker?

To become a chip worker, typically one needs a high school diploma or equivalent, along with technical skills related to electronics or manufacturing. Relevant experience or certifications in semiconductor fabrication, cleanroom procedures, or equipment operation can improve job prospects. Entry-level positions often require attention to detail and adherence to safety protocols in a controlled environment.
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Cities with the most Chip job openings:

What are the most commonly searched types of Chip jobs?

The most popular types of Chip jobs are:

What states have the most Chip jobs?

States with the most job openings for Chip jobs include:

What job categories do people searching Chip jobs look for?

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Infographic showing various Chip job openings in the United States as of September 2026, with employment types broken down into 100% Full Time. Highlights an 100% In-person job distribution.

ASIC Chip Design Lead

Saratoga, CA • On-site

Eridu AI
See more jobs at Eridu AIexternal

$250K - $280K/yr

Full-time

Re-posted 13 days ago

Job description

About Eridu
Eridu is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers to deliver Faster AI. Today's AI performance is frequently limited by communication bottlenecks. Eridu introduces multiple industry-first innovations across silicon, packaging, software, and systems to deliver an order of magnitude improvement in performance and unlock greater GPU utilization to speed training job completion times and tokens-per-second for more profitable inference. We do this while simultaneously reducing capital and power costs and improving reliability.
The company's solutions and value proposition have been widely validated by leading hyperscalers.
Eridu has raised over $200M to date including its most recent, oversubscribed Series A round. The company is led by a veteran team of Silicon Valley executives who have delivered multiple billion dollar product lines and led multiple companies to billion dollar exits, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (the world's leading micro-LED company). The company is in execution mode and has a world-class engineering team with decades of experience in state-of-the-art silicon, packaging, optics, software, and systems. Eridu is working with best-in-class supply chain partners including silicon, packaging and systems.
Visit our website eridu.ai to learn more.
Position Overview
We are seeking a hands-on ASIC Chip Design Lead to own chip design execution from micro-architecture through full-chip integration and timing signoff. This role sits between senior individual contributor and technical lead: you will personally drive RTL and micro-architecture while providing execution leadership across design, verification, and physical design teams.
This is a highly technical, roll-up-your-sleeves role for someone who has taken chips to tape-out, understands what breaks late in the cycle, and knows how to drive designs to closure in a fast-paced startup environment.
Responsibilities
Hands-on RTL Development
  • Write, review, and debug production-quality RTL in Verilog/SystemVerilog
  • Own RTL blocks end-to-end from specification through signoff
  • Make timing-, area-, and power-aware design decisions at the RTL and micro-architecture levels
  • Perform detailed code reviews and set a high technical bar for RTL quality
Micro-Architecture Specification
  • Draft detailed micro-architecture specifications derived from architecture documents and feature requirements
  • Translate high-level requirements into implementable pipelines, control logic, datapaths, interfaces, and corner-case handling
  • Clearly define performance, latency, and resource tradeoffs to unblock RTL and verification execution
Physical-Design-Aware Design & Timing Closure
  • Work closely with Physical Design to improve synthesis and place-and-route timing.
  • Iterate on RTL, hierarchy, micro-architecture, and floorplanning to address timing, congestion, and QoR issues
  • Analyze synthesis and P&R reports and proactively drive timing, area, and power improvements
Verification Collaboration & Debug
  • Partner with Design Verification to debug functional and performance issues
  • Review functional and code coverage and provide actionable feedback
  • Own bugs from discovery through fix, validation, and closure
Full-Chip Integration & Signoff
  • Own full-chip RTL integration and block roll-up
  • Run chip-level synthesis, define constraints, and close chip-level timing
  • Deliver timing-clean netlists to Physical Design that meet performance targets
Execution Discipline & Technical Leadership
  • Drive block- and chip-level design checklists as execution quality gates
  • Review checklist status with designers and proactively push closure of open items
  • Continuously refine design methodologies, checklists, and flows based on silicon learnings
  • Lead by technical authority and hands-on execution rather than coordination alone

Qualifications
  • Strong hands-on experience with RTL design and micro-architecture
  • Proven experience with full-chip integration and timing closure
  • Led at least one full-chip tape-out within the last 3 years, with direct responsibility for design signoff and PD handoff
  • Deep understanding of synthesis, static timing analysis, and physical-design collaboration
  • Experience refactoring and restructuring RTL to resolve timing, area, and congestion challenges
  • Comfortable working cross-functionally with architecture, verification, firmware, and physical design teams
  • Demonstrated ability to drive execution in ambiguous, fast-moving environments

Nice to Have
  • Silicon bring-up experience, including post-silicon debug and RTL-to-silicon correlation
  • Hands-on experience defining and refining SDC constraints and improving post-layout timing
  • Knowledge of high-performance networking architectures and Ethernet-based systems
  • Familiarity with Ultra Ethernet and/or UCIe chip-to-chip interconnect protocols
  • Experience with chiplet-based system design

Why Join Us?
At Eridu, you'll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI infrastructure solutions, transforming the performance of AI data centers.
The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.
Notice to Recruiting Agencies
Eridu does not accept unsolicited resumes or candidate profiles from staffing agencies or third-party recruiters. Any candidate submitted to Eridu without prior written authorization from our recruiting team will be considered unsolicited and will become the property of Eridu. Eridu reserves the right to pursue and hire such candidates without any obligation to pay fees. Recruiting agencies are expressly instructed not to contact hiring managers, employees, or executives regarding open positions.
The pay range for this role is:
250,000 - 280,000 USD per year (Saratoga, CA)

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