A tech pioneering company in Mountain View seeks a Head of Chip Architecture to lead and mentor a team in developing innovative photonics products. This role requires a Ph.D. and over 10 years of ...
A tech pioneering company in Mountain View seeks a Head of Chip Architecture to lead and mentor a team in developing innovative photonics products. This role requires a Ph.D. and over 10 years of ...
Knowledge about chip connection fabrics such UCIe, UAL, LPDDR, HBM3/4 and PCIe Minimum ... Experience in SoC architecture and power/clock/bus design * Experience in DRAM/FLASH architecture ...
Knowledge about chip connection fabrics such UCIe, UAL, LPDDR, HBM3/4 and PCIe Minimum ... Experience in SoC architecture and power/clock/bus design * Experience in DRAM/FLASH architecture ...
Senior D2D Architect
San Jose, CA · On-site
$116 - $287/hr
Research and craft architecture solutions for die-to-die and chip-to-chip communication, optimizing for performance, area, power, security, and resiliency. * Work with other design teams to define ...
Senior D2D Architect
San Jose, CA · On-site
$116 - $287/hr
Research and craft architecture solutions for die-to-die and chip-to-chip communication, optimizing for performance, area, power, security, and resiliency. * Work with other design teams to define ...
Chip Architecture & Integration: Define top-level chip architecture, partition responsibilities across hard and soft IP blocks, and own the integration of hard macros alongside third-party soft IP.
Chip Architecture & Integration: Define top-level chip architecture, partition responsibilities across hard and soft IP blocks, and own the integration of hard macros alongside third-party soft IP.
Chip Architecture & Integration: Define top-level chip architecture, partition responsibilities across hard and soft IP blocks, and own the integration of hard macros alongside third-party soft IP.
Chip Architecture & Integration: Define top-level chip architecture, partition responsibilities across hard and soft IP blocks, and own the integration of hard macros alongside third-party soft IP.
Asic Chip Lead-Full Time- Onsite
Brooklyn Park, MN · On-site
$145K - $205K/yr
Chip Architecture and Development: * Lead the architectural design of ASICs based on high-level requirements and block diagrams. * Collaborate with system architects to define chip functionality ...
Asic Chip Lead-Full Time- Onsite
Brooklyn Park, MN · On-site
$145K - $205K/yr
Chip Architecture and Development: * Lead the architectural design of ASICs based on high-level requirements and block diagrams. * Collaborate with system architects to define chip functionality ...
You'll collaborate closely with architecture, verification, physical design, applications, and ... Chip Architecture and Development: - Lead the architectural design of ASICs based on high-level ...
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You'll collaborate closely with architecture, verification, physical design, applications, and ... Chip Architecture and Development: - Lead the architectural design of ASICs based on high-level ...
ASIC Chip Lead and Design Engineer
Minneapolis, MN · On-site
$180 - $240/hr
You'll collaborate closely with architecture, verification, physical design, applications, and ... Chip Architecture and Development: * Lead the architectural design of ASICs based on high-level ...
ASIC Chip Lead and Design Engineer
Minneapolis, MN · On-site
$180 - $240/hr
You'll collaborate closely with architecture, verification, physical design, applications, and ... Chip Architecture and Development: * Lead the architectural design of ASICs based on high-level ...
We are now looking for a Senior I/O Architect for our NVLink chip to chip team. NVIDIA is seeking an experienced technical leader passionate about defining advanced chip interconnects and protocols.
We are now looking for a Senior I/O Architect for our NVLink chip to chip team. NVIDIA is seeking an experienced technical leader passionate about defining advanced chip interconnects and protocols.
Senior I/O Subsystem Architect
Santa Clara, CA · On-site
$224 - $356.50/hr
We are seeking a Senior I/O Architect for our NVLink chip to chip team. The role involves defining next‑generation communications standards and products based on NVLink technology. Responsibilities
Senior I/O Subsystem Architect
Santa Clara, CA · On-site
$224 - $356.50/hr
We are seeking a Senior I/O Architect for our NVLink chip to chip team. The role involves defining next‑generation communications standards and products based on NVLink technology. Responsibilities
We are now looking for a Senior I/O Architect for our NVLink chip to chip team! NVIDIA is seeking an experienced technical leader passionate about defining advanced chip interconnects and protocols.
We are now looking for a Senior I/O Architect for our NVLink chip to chip team! NVIDIA is seeking an experienced technical leader passionate about defining advanced chip interconnects and protocols.
We are now looking for a Senior I/O Architect for our NVLink chip to chip team! NVIDIA is seeking an experienced technical leader passionate about defining advanced chip interconnects and protocols.
We are now looking for a Senior I/O Architect for our NVLink chip to chip team! NVIDIA is seeking an experienced technical leader passionate about defining advanced chip interconnects and protocols.
Display Silicon Architect
$184K - $324K/yr
Description As a Display Silicon Architect owning the chip architecture and specification in a chip design, you will have responsibilities spanning all aspects of display silicon design: • ...
Display Silicon Architect
$184K - $324K/yr
Description As a Display Silicon Architect owning the chip architecture and specification in a chip design, you will have responsibilities spanning all aspects of display silicon design: • ...
Senior Architect, NVLink
Westford, MA · On-site
Researching and crafting architecture solutions for chip-to-chip communication, optimizing for performance, area, power, security, and resiliency * Working with other design teams to define ...
Senior Architect, NVLink
Westford, MA · On-site
Researching and crafting architecture solutions for chip-to-chip communication, optimizing for performance, area, power, security, and resiliency * Working with other design teams to define ...
Senior Architect, NVLink
Westford, MA · On-site
NVIDIA is seeking an experienced technical leader passionate about defining advanced chip ... Researching and crafting architecture solutions for chip-to-chip communication, optimizing for ...
Senior Architect, NVLink
Westford, MA · On-site
NVIDIA is seeking an experienced technical leader passionate about defining advanced chip ... Researching and crafting architecture solutions for chip-to-chip communication, optimizing for ...
Senior Architect, NVLink
Westford, MA · On-site
Researching and crafting architecture solutions for chip-to-chip communication, optimizing for performance, area, power, security, and resiliency * Working with other design teams to define ...
Senior Architect, NVLink
Westford, MA · On-site
Researching and crafting architecture solutions for chip-to-chip communication, optimizing for performance, area, power, security, and resiliency * Working with other design teams to define ...
Minimum Qualifications BS degree Experience in chip architecture, display subsystem architecture and/or design SoC display subsystem architecture and micro-architecture experience Preferred ...
Minimum Qualifications BS degree Experience in chip architecture, display subsystem architecture and/or design SoC display subsystem architecture and micro-architecture experience Preferred ...
Display Silicon Architect
Cupertino, CA · On-site
$185 - $325/hr
Description As a Display Silicon Architect owning the chip architecture and specification in a chip design, you will have responsibilities spanning all aspects of display silicon design:
Display Silicon Architect
Cupertino, CA · On-site
$185 - $325/hr
Description As a Display Silicon Architect owning the chip architecture and specification in a chip design, you will have responsibilities spanning all aspects of display silicon design:
$210 - $360/hr
About Architect Architect is a frontier AI lab for chip design. We build AI models and tools for on-demand custom ASICs at scale. Our goal is to co-design custom ASICs alongside evolving ML workloads ...
New
$210 - $360/hr
About Architect Architect is a frontier AI lab for chip design. We build AI models and tools for on-demand custom ASICs at scale. Our goal is to co-design custom ASICs alongside evolving ML workloads ...
New
Microarchitect / RTL Design - On-Chip Interconnect & High-Speed Fabric Design
Palo Alto, CA · On-site
$210 - $360/hr
About Architect Architect is a frontier AI lab for chip design. We build AI models and tools for on-demand custom ASICs at scale. Our goal is to co-design custom ASICs alongside evolving ML workloads ...
Microarchitect / RTL Design - On-Chip Interconnect & High-Speed Fabric Design
Palo Alto, CA · On-site
$210 - $360/hr
About Architect Architect is a frontier AI lab for chip design. We build AI models and tools for on-demand custom ASICs at scale. Our goal is to co-design custom ASICs alongside evolving ML workloads ...
Chip Architect information
See salary details
$46.5K - $60.6K
3% of jobs
$60.6K - $74.7K
4% of jobs
$74.7K - $88.8K
17% of jobs
$89.7K is the 25th percentile. Wages below this are outliers.
$88.8K - $102.9K
17% of jobs
The median wage is $114.4K / yr.
$102.9K - $117K
11% of jobs
$117K - $131K
4% of jobs
$131K - $145.1K
4% of jobs
$145.1K - $159.2K
3% of jobs
$164.1K is the 75th percentile. Wages above this are outliers.
$159.2K - $173.3K
33% of jobs
$173.3K - $187.4K
1% of jobs
$187.4K - $201.5K
2% of jobs
$46.5K
$128.8K
$201.5K
How much do chip architect jobs pay per year?
As of Sep 3, 2026, the average yearly pay for chip architect in the United States is $128,756.00, according to ZipRecruiter salary data. Most workers in this role earn between $91,000.00 and $166,000.00 per year, depending on experience, location, and employer.
What are the key skills and qualifications needed to thrive as a chip architect?
To thrive as a Chip Architect, you need deep expertise in computer architecture, digital circuit design, and strong analytical skills, usually supported by an advanced degree in electrical engineering or a related field. Familiarity with hardware description languages (like Verilog or VHDL), EDA tools, and simulation platforms is essential, along with knowledge of industry-standard protocols. Strong problem-solving abilities, effective communication, and leadership skills set outstanding chip architects apart when collaborating across multidisciplinary teams. These competencies are crucial for designing efficient, innovative chips that meet performance, power, and cost requirements in a highly competitive technology industry.
What are some common challenges faced by chip architects when translating system requirements into chip designs?
Chip Architects often face the challenge of balancing performance, power consumption, and cost constraints while translating high-level system requirements into detailed chip architectures. They must ensure that their designs can be efficiently implemented in silicon, taking into account factors like manufacturability, scalability, and integration with existing hardware and software. Collaborating closely with cross-functional teams—such as hardware, software, and verification engineers—is essential to address issues early and ensure alignment throughout the development process. Staying updated with rapidly evolving semiconductor technologies and industry standards is also a key part of overcoming these challenges.
What is the difference between Chip Architect vs Hardware Design Engineer?
| Aspect | Chip Architect | Hardware Design Engineer |
|---|---|---|
| Required Credentials | Bachelor's or Master's in Electrical Engineering, Computer Engineering, or related fields; experience in chip design and architecture | Bachelor's or Master's in Electrical Engineering, Computer Engineering, or related fields; focus on circuit design and implementation |
| Work Environment | Design teams, R&D labs, collaborative project settings | Design labs, testing facilities, manufacturing environments |
| Employer & Industry Usage | Semiconductor companies, tech firms, integrated circuit manufacturers | Electronics companies, semiconductor firms, hardware development labs |
The main difference is that a Chip Architect focuses on designing the overall architecture and high-level specifications of chips, while a Hardware Design Engineer concentrates on implementing circuit designs based on specifications. Both roles require electrical engineering expertise, but the Chip Architect is more involved in conceptual and architectural decisions, whereas the Hardware Design Engineer handles detailed circuit development and testing.
What does a chip architect do?
A chip architect designs the overall structure and specifications of integrated circuits, including processors and other hardware components. They analyze performance requirements, create architectural models, and collaborate with engineers to ensure the design meets technical and functional goals, often using tools like CAD software and simulation environments.
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Cities with the most Chip Architect job openings:
What states have the most Chip Architect jobs?
States with the most job openings for Chip Architect jobs include:
What job categories do people searching Chip Architect jobs look for?
The top searched job categories for Chip Architect jobs are:
Head of Chip Architecture - Photonics Interconnects Leader (Mountain View)
Victorville, CA • On-site
Full-time
Re-posted 2 days ago
Job description
A tech pioneering company in Mountain View seeks a Head of Chip Architecture to lead and mentor a team in developing innovative photonics products. This role requires a Ph.D. and over 10 years of relevant experience. Responsibilities include defining chip architectures, collaborating with engineering teams, and communicating complex technical concepts to various stakeholders. A competitive compensation package along with comprehensive benefits reflects the company's commitment to innovation and excellence.
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