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Chip Architect Jobs (NOW HIRING)

Apple

Digital Architect

Austin, TX · On-site

... chip architecture and/or digital design is desirable, preferably in touch or communications.Experience developing and launching high volume IC designsStrong electrical engineering background in ...

Apple

Digital Architect

Austin, TX · On-site

... chip architecture and/or digital design is desirable, preferably in touch or communications.Experience developing and launching high volume IC designsStrong electrical engineering background in ...

Eridu AI

ASIC Chip Design Lead

Saratoga, CA · On-site

$250K - $280K/yr

Draft detailed micro-architecture specifications derived from architecture documents and feature ... Run chip-level synthesis, define constraints, and close chip-level timing * Deliver timing-clean ...

Jobsbridge

ASIC Engineer

San Jose, CA

$194K/yr

ASIC Design, FPGA, RTL Design, Chip Architecture, ASIC, Implementation,Synthesis /Conformal (Cadence Tool for formal verification) Description: Should have 2-5 years of experience in FPGA/ASIC ...

Astera Labs

Chip Lead, Senior Director

San Jose, CA · On-site

This is an executive technical leadership role where you will connect architecture, design ... Drive chip development execution from RTL to GDSII, ensuring architecture, implementation, and ...

Apple

GPU Benchmark Analysis Architect

Cupertino, CA · On-site

$206K/yr

You'll collaborate with engineers across Apple to design how all of our technologies work in unison, drive development of our renowned system-on-a-chip architecture and develop forward-looking ...

Apple

GPU Benchmark Analysis Architect

Cupertino, CA · On-site

$206K/yr

You'll collaborate with engineers across Apple to design how all of our technologies work in unison, drive development of our renowned system-on-a-chip architecture and develop forward-looking ...

Astera Labs

Chip Lead, Senior Director

San Jose, CA · On-site

This is an executive technical leadership role where you will connect architecture, design ... Drive chip development execution from RTL to GDSII, ensuring architecture, implementation, and ...

Normal Computing

Silicon Architect

New York, NY · On-site

$234K - $298K/yr

If the appeal of working on a chip that has to be invented is greater to you than iterating on one that already exists, keep reading. Responsibilities * Help define the architecture and ...

Altera

Clocking Architect

San Jose, CA

$76 - $99.50/hr

Clocking Architecture & Full-Chip Strategy * Own and drive the complete clocking architecture for Altera's FPGA/SoC devices, including clock tree topology, domain partitioning, frequency planning ...

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Chip Architect information

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$46.5K

$128.8K

$201.5K

How much do chip architect jobs pay per year?

As of Jun 6, 2026, the average yearly pay for chip architect in the United States is $128,756.00, according to ZipRecruiter salary data. Most workers in this role earn between $91,000.00 and $166,000.00 per year, depending on experience, location, and employer.

What are some common challenges faced by Chip Architects when translating system requirements into chip designs?

Chip Architects often face the challenge of balancing performance, power consumption, and cost constraints while translating high-level system requirements into detailed chip architectures. They must ensure that their designs can be efficiently implemented in silicon, taking into account factors like manufacturability, scalability, and integration with existing hardware and software. Collaborating closely with cross-functional teams—such as hardware, software, and verification engineers—is essential to address issues early and ensure alignment throughout the development process. Staying updated with rapidly evolving semiconductor technologies and industry standards is also a key part of overcoming these challenges.

What does a Chip Architect do?

A Chip Architect is responsible for designing the overall structure and functionality of integrated circuits or microchips. They define the chip's architecture, specifying how different components such as processors, memory, and interfaces work together to achieve desired performance, power, and area targets. Chip Architects collaborate with hardware engineers, software developers, and verification teams to ensure the final product meets technical specifications and industry standards. Their work is crucial for developing advanced electronics used in computers, smartphones, and other digital devices.

What is the difference between Chip Architect vs Hardware Design Engineer?

AspectChip ArchitectHardware Design Engineer
Required CredentialsBachelor's or Master's in Electrical Engineering, Computer Engineering, or related fields; experience in chip design and architectureBachelor's or Master's in Electrical Engineering, Computer Engineering, or related fields; focus on circuit design and implementation
Work EnvironmentDesign teams, R&D labs, collaborative project settingsDesign labs, testing facilities, manufacturing environments
Employer & Industry UsageSemiconductor companies, tech firms, integrated circuit manufacturersElectronics companies, semiconductor firms, hardware development labs

The main difference is that a Chip Architect focuses on designing the overall architecture and high-level specifications of chips, while a Hardware Design Engineer concentrates on implementing circuit designs based on specifications. Both roles require electrical engineering expertise, but the Chip Architect is more involved in conceptual and architectural decisions, whereas the Hardware Design Engineer handles detailed circuit development and testing.

What are the key skills and qualifications needed to thrive as a Chip Architect, and why are they important?

To thrive as a Chip Architect, you need deep expertise in computer architecture, digital circuit design, and strong analytical skills, usually supported by an advanced degree in electrical engineering or a related field. Familiarity with hardware description languages (like Verilog or VHDL), EDA tools, and simulation platforms is essential, along with knowledge of industry-standard protocols. Strong problem-solving abilities, effective communication, and leadership skills set outstanding chip architects apart when collaborating across multidisciplinary teams. These competencies are crucial for designing efficient, innovative chips that meet performance, power, and cost requirements in a highly competitive technology industry.
More about Chip Architect jobs
What cities are hiring for Chip Architect jobs? Cities with the most Chip Architect job openings:
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Chip Architect jobs near you
Infographic showing various Chip Architect job openings in the United States as of May 2026, with employment types broken down into 79% Full Time, 4% Part Time, and 17% Contract. Highlights an 95% Physical, 2% Hybrid, and 3% Remote job distribution, with an average salary of $128,756 per year, or $61.9 per hour.
Principal Silicon Performance Architect

Principal Silicon Performance Architect

Microsoft

Redmond, WA • On-site

$220K - $331K/yr

Full-time

Posted 7 days ago

Microsoft rating

8.6

Company rating: 8.6 out of 10

Based on 125 frontline employees who took The Breakroom Quiz

47th of 186 rated software companies

Job description

Overview
We are forming a small, agile engineering team to accelerate a new initiative focused on artificial intelligence (AI) performance - from micro-architecture exploration through end-to-end workload validation. You'll work at the intersection of silicon, systems, and software, partnering cross-functionally with chip and system architects, as well as inference software engineers to drive data-backed design decisions and deliver step-function improvements in throughput, latency, and efficiency.
As a Principal Silicon Performance Architect on this AI acceleration effort, you will own performance modeling and analysis for current and future AI workloads. You will translate hardware and software architectural ideas into simulator implementations, run rigorous experiments across design variants, and turn results into clear guidance for architecture and product decisions.
Microsoft's mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.
Responsibilities
• Extend and adapt simulation infrastructure to model new micro-architecture innovations for AI inference.
• Analyze performance for current and forward-looking AI inference workloads across latency, throughput, and efficiency dimensions.
• Drive design-space exploration using AI-assisted workflows, automation, and large-scale experiment generation.
• Communicate performance insights clearly and influence architecture decisions through data-driven recommendations.
• Collaborate closely with chip, system, and software architects to propose, evaluate, and iterate on architectural variations.
Qualifications
Required/Minimum Qualifications:
  • Bachelor's Degree in Computer Science or related technical field AND 8+ years technical engineering experience with coding in languages including, but not limited to C/C++, Python
    • OR equivalent experience.

Other Requirements:
  • Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings:
    • Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Preferred Qualifications:
  • Advanced Degree (Master's, Ph.D.) in Electrical Engineering, Computer Engineering, or related field.
  • Experience in chip architecture or micro-architecture analysis at the logical level, including memory, functional units, memory controllers, and Input/Output (I/O) controllers.
  • Experience in performance engineering, including profiling, bottleneck analysis, experimental design, and micro-architecture trade-off analysis.
  • Experience using performance modeling or simulation to evaluate hardware/software trade-offs across chip, system, and software teams.
  • Experience with AI inference acceleration features and accelerator or Graphics Processing Unit (GPU) performance analysis.
  • Experience with the AI inference software stack, including compilers, runtimes, and model serving systems.
  • Experience modifying architectural simulators or performance modeling codebases (e.g., C, C++, or Python).

Software Engineering IC6 - The typical base pay range for this role across the U.S. is USD $163,000 - $296,400 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $220,800 - $331,200 per year.
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
https://careers.microsoft.com/us/en/us-corporate-pay
This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.
Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

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About Microsoft

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Our infrastructure is comprised of a large global portfolio of more than 100 datacenters and 1 million servers. Our foundation is built upon and managed by a team of subject matter experts working to support services for more than 1 billion customers and 20 million businesses in over 90 countries worldwide. With environmental sustainability and optimization at the forefront of our datacenter design and operations, we continue to grow and evolve as we meet the ever-changing business demands that hold Microsoft as a world-class cloud provider.

Industry

Computer and computer peripheral equipment and software wholesalers

Company size

10,000+ Employees

Headquarters location

Redmond, WA, US

Year founded

1975

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