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Chip Architect Jobs in California (NOW HIRING)

P3Hired

Wireless Chip Architect

Mountain View, CA

$75 - $98.75/hr

As a Wireless Architect, you drive the definition of connectivity subsystem architectures for next-generation products including Wi-Fi, Bluetooth, and UWB with mixed analog/digital hardware. You will ...

Ceva

Wireless Chip Architect

Mountain View, CA · On-site +1

$75 - $98.75/hr

As a Wireless Architect, you drive the definition of connectivity subsystem architectures for next-generation products including Wi-Fi, Bluetooth, and UWB with mixed analog/digital hardware. You will ...

Apple

Display Silicon Architect

Cupertino, CA · On-site

Description As a Display Silicon Architect owning the chip architecture and specification in a chip design, you will have responsibilities spanning all aspects of display silicon design: • ...

Nvidia

Senior I/O Subsystem Architect

Santa Clara, CA · Hybrid

We are now looking for a Senior I/O Architect for our NVLink chip to chip team. NVIDIA is seeking an experienced technical leader passionate about defining advanced chip interconnects and protocols.

Nvidia

Senior I/O Subsystem Architect

Santa Clara, CA · Hybrid

We are now looking for a Senior I/O Architect for our NVLink chip to chip team! NVIDIA is seeking an experienced technical leader passionate about defining advanced chip interconnects and protocols.

Apple

Display Silicon Architect

Cupertino, CA

$184K - $324K/yr

Description As a Display Silicon Architect owning the chip architecture and specification in a chip design, you will have responsibilities spanning all aspects of display silicon design: • ...

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All JobsChip Architect JobsChip Architect Jobs in California

Chip Architect information

See California salary details

$45.9K

$127.1K

$198.9K

How much do chip architect jobs pay per year?

As of Sep 3, 2026, the average yearly pay for chip architect in California is $127,070.00, according to ZipRecruiter salary data. Most workers in this role earn between $89,800.00 and $163,800.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a chip architect?

To thrive as a Chip Architect, you need deep expertise in computer architecture, digital circuit design, and strong analytical skills, usually supported by an advanced degree in electrical engineering or a related field. Familiarity with hardware description languages (like Verilog or VHDL), EDA tools, and simulation platforms is essential, along with knowledge of industry-standard protocols. Strong problem-solving abilities, effective communication, and leadership skills set outstanding chip architects apart when collaborating across multidisciplinary teams. These competencies are crucial for designing efficient, innovative chips that meet performance, power, and cost requirements in a highly competitive technology industry.

What are some common challenges faced by chip architects when translating system requirements into chip designs?

Chip Architects often face the challenge of balancing performance, power consumption, and cost constraints while translating high-level system requirements into detailed chip architectures. They must ensure that their designs can be efficiently implemented in silicon, taking into account factors like manufacturability, scalability, and integration with existing hardware and software. Collaborating closely with cross-functional teams—such as hardware, software, and verification engineers—is essential to address issues early and ensure alignment throughout the development process. Staying updated with rapidly evolving semiconductor technologies and industry standards is also a key part of overcoming these challenges.

What is the difference between Chip Architect vs Hardware Design Engineer?

AspectChip ArchitectHardware Design Engineer
Required CredentialsBachelor's or Master's in Electrical Engineering, Computer Engineering, or related fields; experience in chip design and architectureBachelor's or Master's in Electrical Engineering, Computer Engineering, or related fields; focus on circuit design and implementation
Work EnvironmentDesign teams, R&D labs, collaborative project settingsDesign labs, testing facilities, manufacturing environments
Employer & Industry UsageSemiconductor companies, tech firms, integrated circuit manufacturersElectronics companies, semiconductor firms, hardware development labs

The main difference is that a Chip Architect focuses on designing the overall architecture and high-level specifications of chips, while a Hardware Design Engineer concentrates on implementing circuit designs based on specifications. Both roles require electrical engineering expertise, but the Chip Architect is more involved in conceptual and architectural decisions, whereas the Hardware Design Engineer handles detailed circuit development and testing.

What does a chip architect do?

A chip architect designs the overall structure and specifications of integrated circuits, including processors and other hardware components. They analyze performance requirements, create architectural models, and collaborate with engineers to ensure the design meets technical and functional goals, often using tools like CAD software and simulation environments.

What are popular job titles related to Chip Architect jobs in California?

For Chip Architect jobs in California, the most frequently searched job titles are:

What job categories do people searching Chip Architect jobs in California look for?

The top searched job categories for Chip Architect jobs in California are:

What cities in California are hiring for Chip Architect jobs?

Cities in California with the most Chip Architect job openings:

Chip Architect jobs near you
Infographic showing various Chip Architect job openings in California as of August 2026, with employment types broken down into 91% Full Time, 5% Part Time, and 4% Contract. Highlights an 78% Physical, 8% Hybrid, and 14% Remote job distribution, with an average salary of $127,070 per year, or $61.1 per hour.

Wireless Chip Architect

P3Hired

Mountain View, CA

$75 - $98.75/hr

Full-time

Re-posted 27 days ago

Job description

Position Overview

Ceva is at the forefront of the Smart Edge revolution, with innovative state-of-the-art Silicon and Software solutions that enable products to Connect, Sense and Infer. Our advanced wireless technologies, including Bluetooth, Wi-Fi, UWB, and Cellular IoT, are integrated into over a Billion devices annually. We are offering you a unique opportunity to shape and make a great impact on the roadmap of connected devices.

In this role, you will be at the intersection of cutting-edge wireless technology and direct customer engagement. As a Wireless Architect, you drive the definition of connectivity subsystem architectures for next-generation products including Wi-Fi, Bluetooth, and UWB with mixed analog/digital hardware. You will also serve as a key technical partner for our customers, leading technical pre-sales, co-develop joint solution offerings, and bring a creative, flexible mindset to solving complex real-world connectivity challenges. This requires both architectural depth and strong product engineering experience, from concept through productization.

Responsibilities

Drive full-system view of how the connectivity subsystem interacts within an SoC, including CPU/processor, memory, and peripheral interfaces

Definition of connectivity subsystem architecture specifications including :

  • Feature-set definition and PPA (Power, Performance, Area) targets

  • Definition of system low power modes and PMU requirements

  • Definition of HW and SW interfaces of the connectivity sub-systems including: HW interfaces, state machines, operation sequences, etc.

  • Analog and digital domains partitioning

Customer Facing and Technical Engagement

  • Lead technical discussions with customers, presenting connectivity architecture options and value propositions

  • Co-develop joint solution offerings with customers and partners, acting as technical advisor during system integration phases

Support Product Lifecycle and Productization

  • Support post-tape-out testing, production validation, and productization of wireless connectivity solutions

  • Lead or contribute to production-readiness activities including silicon characterization, yield analysis, and qualification testing

Cross-functional Leadership

  • Work closely with logic design, physical design, firmware, and validation teams to ensure successful implementation

  • Support wireless subsystem integration process from architectural definition through implementation, lab integration and test coverage planning

  • Collaborate with product management and business development stakeholders to translate customer feedback into architectural requirements and product roadmap inputs

Qualifications

  • B.Sc. or M.Sc in Electrical Engineering

  • Deep understanding of full-system SoC architecture, with emphasis on how connectivity subsystems interact with processors, memory controllers, power domains, and software stacks

  • Product engineering experience: deep understanding of full lifecycle including post tape-out testing, silicon bring-up, productization, and production qualification.

  • Experience in system definition for wireless communication systems

  • Experience in wireless communication standards (such as WiFi/BT/Cellular/UWB)

  • Experience in ASIC design and architecture, with proven experience in successful tape-outs and production

  • Knowledge in performance and power modeling and analysis

  • Deep understanding of VLSI development process and methods

  • Technical leadership

  • Strong communicator, able to translate complex architectural concepts for customers, executives, and engineering teams.

  • Creative and flexible mindset: comfortable navigating ambiguous requirements and proposing pragmatic, innovative solutions

  • Proven customer facing experience. Leading technical discussion, building trust, and influencing design decisions.

  • Knowledge in RF integration and performance optimization

  • Previous experience with 3rd party IP integration

  • Knowledge in CPU/Processor architecture