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Asic Verification Jobs in Minnesota (NOW HIRING)

Geologics

Advanced ASIC/FPGA Engineer

Bloomington, MN · On-site

$75 - $81/hr

Responsible for definition, design, verification and documentation for ASIC (Application Specific Integrated Circuit) and/or FPGA (Field Programmable Gate Array) developments * Determines ...

Geologics

Advanced ASIC/FPGA Engineer

Bloomington, MN · On-site

$75 - $81/hr

Responsible for definition, design, verification and documentation for ASIC (Application Specific Integrated Circuit) and/or FPGA (Field Programmable Gate Array) developments * Determines ...

Micron

Sr. Design Verification Engineer

Minneapolis, MN · On-site

$142K - $173K/yr

Our ASIC Design Verification team develops robust, scalable verification environments for highly complex designs and partners closely with global design teams to deliver highquality silicon on ...

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All JobsAsic Verification JobsAsic Verification Jobs in Minnesota

Asic Verification information

See Minnesota salary details

$86.2K

$152.9K

$202.7K

How much do asic verification jobs pay per year?

As of Sep 3, 2026, the average yearly pay for asic verification in Minnesota is $152,863.00, according to ZipRecruiter salary data. Most workers in this role earn between $133,200.00 and $171,900.00 per year, depending on experience, location, and employer.

What is ASIC verification?

ASIC verification is the process of ensuring that an Application-Specific Integrated Circuit (ASIC) design functions as intended before it is manufactured. It involves using simulation, formal methods, and other verification techniques to catch and correct design errors early, which helps prevent costly mistakes during chip fabrication. Verification engineers create test environments and write testbenches to simulate the ASIC's behavior under different scenarios. This step is critical in the chip design flow, as it directly impacts the quality, reliability, and performance of the final product.

What are the key skills and qualifications needed to thrive as an ASIC verification engineer?

To thrive as an ASIC Verification Engineer, you need a strong background in digital design, verification methodologies, and hardware description languages such as Verilog or VHDL, often supported by a degree in electrical engineering or a related field. Familiarity with industry-standard verification tools like UVM, SystemVerilog, and simulation or formal verification environments is typically expected. Analytical thinking, attention to detail, and effective communication are essential soft skills for diagnosing complex issues and collaborating with design teams. Mastery of these skills ensures high-quality, error-free ASIC designs and efficient project delivery in a highly technical environment.

What are some common challenges faced in ASIC verification, and how can new team members effectively overcome them?

A common challenge in ASIC Verification is ensuring comprehensive test coverage to catch subtle design bugs before production. New team members often need to quickly familiarize themselves with complex verification environments and tools such as UVM, SystemVerilog, and simulation platforms. Collaborating closely with design engineers and participating in regular code and coverage reviews can accelerate learning and help resolve issues efficiently. Seeking mentorship from experienced colleagues and actively engaging in team discussions also aids in navigating verification complexities.

What is the difference between Asic Verification vs FPGA Verification?

AspectAsic VerificationFPGA Verification
Required CredentialsBachelor's/Master's in Electrical Engineering or Computer Engineering, knowledge of hardware description languages (HDL)Bachelor's/Master's in Electrical Engineering or Computer Engineering, HDL knowledge
Work EnvironmentDesign teams, hardware labs, simulation environmentsPrototyping labs, hardware testing, simulation
Industry UsageSemiconductor companies, chip design firmsPrototyping, FPGA-based product development
Common Search/ComparisonAsic Verification vs FPGA Verification

Asic Verification and FPGA Verification share similar skills, such as HDL knowledge and hardware testing. However, Asic Verification focuses on validating integrated circuit designs before manufacturing, often involving complex simulation and formal verification. FPGA Verification involves testing programmable hardware prototypes, emphasizing rapid prototyping and hardware-in-the-loop testing. Both roles are essential in hardware development but differ in scope, environment, and end goals.

How to become an ASIC verification engineer?

To become an ASIC verification engineer, candidates typically need a bachelor's degree in electrical engineering, computer engineering, or a related field. Gaining experience with hardware description languages like Verilog or VHDL, and verification tools such as UVM or SystemVerilog, is essential. Developing strong problem-solving skills and understanding digital design principles are also important for success in this role.

What does an ASIC verification engineer do?

An ASIC verification engineer designs and executes tests to ensure that application-specific integrated circuits (ASICs) function correctly according to specifications. They develop test plans, write simulation code using hardware description languages like SystemVerilog, and use verification tools to identify and fix design errors before manufacturing. This role requires strong programming skills, knowledge of digital design, and familiarity with verification methodologies such as UVM.

What are the most commonly searched types of Asic Verification jobs in Minnesota?

The most popular types of Asic Verification jobs in Minnesota are:

What are popular job titles related to Asic Verification jobs in Minnesota?

For Asic Verification jobs in Minnesota, the most frequently searched job titles are:

What job categories do people searching Asic Verification jobs in Minnesota look for?

The top searched job categories for Asic Verification jobs in Minnesota are:

Asic Verification jobs near you
Infographic showing various Asic Verification job openings in Minnesota as of August 2026, with employment types broken down into 1% As Needed, 80% Full Time, 14% Part Time, 3% Contract, and 2% Nights. Highlights an 89% Physical, 3% Hybrid, and 8% Remote job distribution, with an average salary of $152,863 per year, or $73.5 per hour.

ASIC Chip Lead and Design Engineer

Chelsea Search Group

Minneapolis, MN • On-site

$180 - $240/hr

Other

Posted 9 days ago

Job description

ASIC Chip Lead and Design Engineer Job Description:

You'll play a key role in designing and delivering complex, custom ASICs from concept through silicon. This is a highly hands-on opportunity for an engineer who enjoys solving challenging digital design problems and working across the full ASIC/SoC development flow. You'll collaborate closely with architecture, verification, physical design, applications, and business teams to turn demanding technical requirements into high-performance silicon while optimizing for power, performance, and area (PPA). The ideal candidate is a high-aptitude engineer who is currently designing complex digital blocks and has strong, practical experience across the complete ASIC/SoC design lifecycle. Engineers with additional experience in radiation-hardened design, analog/mixed-signal circuits, EDA methodologies, or standard-cell library development will have an opportunity to apply and expand that expertise. Beyond design, you'll help evaluate customer requirements, develop technical approaches and effort estimates for new opportunities, and influence improvements to internal design methodologies and processes.

Essential Duties and Qualifications:
  • Chip Architecture and Development:
    • Lead the architectural design of ASICs based on high-level requirements and block diagrams.
    • Collaborate with system architects to define chip functionality, interfaces, and performance targets.
    • Develop detailed specifications for the chip's components.
  • RTL Design and Synthesis:
    • Use Synopsys Design Compiler to create RTL (Register Transfer Level) designs.
    • Optimize RTL code for area, power, and performance.
    • Implement and verify complex digital blocks.
  • Constraint Development:
    • Develop timing constraints for the entire chip.
    • Work closely with physical design teams to ensure successful place-and-route.
  • RISC Processor Conformance:
    • Constrain and verify RISC processors within the chip.
    • Optimize processor performance and power efficiency.
  • Physical Design Collaboration:
    • Collaborate with physical design teams on floorplanning, placement, and routing.
    • Address any design closure issues.
  • Verification Support:
    • Work with verification engineers to ensure functional correctness.
    • Assist in creating testbenches and verifying the chip’s functionality.
  • Modern revision-control tools and best-practices in a collaborative, multi-site design community.
  • Proficiency with UNIX/Linux incl. shell scripting, text utilities (e.g., sed, awk, grep), using Modules, high-level programming such as C/C++, PERL/Python/TCL scripting.
  • Proficiency with Windows apps, incl. Word, Excel, PowerPoint, Visio, Project, PDF conversion.
Required Qualifications:
  • BSEE/MSEE or equivalent
  • 10+ years of direct industry experience with ASIC and/or SoC design.
  • Proficiency in Synopsys Design Compiler and other EDA tools.
  • Strong understanding of digital design principles.
  • Familiarity with RISC architectures (e.g., ARM, MIPS).
  • Excellent problem-solving skills and attention to detail.
  • A strong background in RTL based digital IC design using Verilog/SystemVerilog.
  • Proven track record of first-pass successes.
  • A self-starter with the ability to assume leadership roles.
  • Ability to work well in a diverse team environment.
  • Willingness to mentor junior engineers.
  • Experience with industry standard development tools and methodologies.
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