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Asic Verification Engineer Jobs in Washington (NOW HIRING)

Next Step Systems

FPGA Engineer

Linthicum, MD · On-site

$128K - $164K/yr

... ASIC/FPGA, create specification documents. - Develop RTL designs using SystemVerilog, with emphasis ... Verify DSP blocks against fixed-point MATLAB model, work in collaboration with systems engineers ...

Next Step Systems

Senior FPGA Engineer

Linthicum, MD · On-site

$128K - $164K/yr

... ASIC/FPGA, create specification documents. - Develop RTL designs using SystemVerilog, with emphasis ... Verify DSP blocks against fixed-point MATLAB model, work in collaboration with systems engineers ...

Next Step Systems

FPGA Electrical Engineer

Linthicum, MD · On-site

... ASIC/FPGA, create specification documents. - Develop RTL designs using SystemVerilog, with emphasis ... Verify DSP blocks against fixed-point MATLAB model, work in collaboration with systems engineers ...

Next Step Systems

Senior FPGA Electrical Engineer

Linthicum, MD · On-site

$102K - $138K/yr

... ASIC/FPGA, create specification documents. - Develop RTL designs using SystemVerilog, with emphasis ... Verify DSP blocks against fixed-point MATLAB model, work in collaboration with systems engineers ...

Ambarella

ASIC Design Engineer Intern

Washington, DC · On-site

$120 - $150/hr

Logic design, implementation, and verification using Verilog, System Verilog, and any required programing and scripting languages. Synthesize and optimize RTL for timing, area and power. Developing ...

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Asic Verification Engineer information

See Washington salary details

$99.7K

$176.8K

$234.4K

How much do asic verification engineer jobs pay per year?

As of Aug 8, 2026, the average yearly pay for asic verification engineer in Washington is $176,772.00, according to ZipRecruiter salary data. Most workers in this role earn between $154,000.00 and $198,800.00 per year, depending on experience, location, and employer.

What is the salary of an ASIC verification engineer?

The salary of an ASIC verification engineer typically ranges from $80,000 to $150,000 annually, depending on experience, location, and company size. Entry-level positions may start lower, while experienced engineers with specialized skills in hardware description languages and verification tools can earn higher salaries.

What are some common challenges faced by ASIC Verification Engineers during the verification process?

ASIC Verification Engineers often encounter challenges such as dealing with complex designs, debugging intricate issues, and ensuring thorough coverage of all design specifications. Coordinating with design and RTL teams to clarify requirements and resolve discrepancies is a frequent part of the job. Additionally, managing tight project timelines while maintaining high verification quality requires effective time management and strong communication skills. Continuous learning is also important, as verification methodologies and tools evolve rapidly in this field.

What are the key skills and qualifications needed to thrive as an ASIC Verification Engineer, and why are they important?

To thrive as an ASIC Verification Engineer, you need a solid background in digital design, computer architecture, and verification methodologies, typically supported by a degree in electrical engineering or a related field. Familiarity with tools and languages like SystemVerilog, UVM, simulation environments, and waveform viewers is essential, and certifications in verification or design may be beneficial. Strong analytical thinking, attention to detail, and effective communication are crucial soft skills for debugging complex designs and collaborating with design teams. These skills and qualities are vital to ensure that ASIC designs are thoroughly tested, compliant with specifications, and delivered with high quality and reliability.

What does an ASIC verification engineer do?

An ASIC verification engineer designs and executes tests to ensure that integrated circuit designs function correctly according to specifications. They develop test plans, write simulation testbenches using hardware description languages like SystemVerilog, and analyze simulation results to identify and fix design issues. This role requires knowledge of digital design, verification tools, and often involves working closely with design engineers throughout the development process.

What is an ASIC Verification Engineer?

An ASIC Verification Engineer is a professional who specializes in testing and validating the design of Application-Specific Integrated Circuits (ASICs) to ensure they function correctly according to specifications. They develop testbenches, write test cases, and use simulation tools to detect and debug design errors before the chip is manufactured. Their work is critical in preventing costly mistakes and ensuring the final product meets performance and reliability standards. ASIC Verification Engineers often collaborate closely with design engineers to understand requirements and resolve issues.

What is the difference between Asic Verification Engineer vs Digital Design Engineer?

AspectAsic Verification EngineerDigital Design Engineer
Primary FocusVerifying ASIC designs for correctness and functionalityDesigning digital circuits and architectures
Skills & CertificationsHardware description languages (HDL), verification tools, scriptingHDL, digital logic, circuit design
Work EnvironmentVerification labs, simulation environmentsDesign teams, CAD tools, prototyping labs
Industry UsageSemiconductor, electronics manufacturingSemiconductor, consumer electronics, computing

While both roles require expertise in HDL and semiconductor industry experience, Asic Verification Engineers focus on testing and validating ASIC designs, ensuring they meet specifications. Digital Design Engineers primarily create and develop digital circuits. Both roles are essential in the chip development process but differ in their core responsibilities and daily tasks.

What is an ASIC Verification Engineer?

An ASIC verification engineer works with system designers and architects to test performance and validate hardware components and systems. You plan and develop a verification environment while coordinating with developers and architects throughout the design process. Your duties involve working closely with these other teams during the design process. Your responsibilities may include using computer hardware languages such as Verilog. In this career, you work on hardware design and use algorithms, data structure analysis, and other advanced design techniques.

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Asic Verification Engineer jobs near you
Infographic showing various Asic Verification Engineer job openings in Washington as of August 2026, with employment types broken down into 92% Full Time, 2% Part Time, and 6% Contract. Highlights an 87% Physical, 4% Hybrid, and 9% Remote job distribution, with an average salary of $176,772 per year, or $85 per hour.

Senior ASIC Physical Design Engineer with Security Clearance

Johns Hopkins University Applied Physics Laboratory

Laurel, MD • On-site

Other

Medical, Dental, Vision, Life, Retirement, PTO

Re-posted 21 days ago

Job description

Description Do you love building and prototyping robust electrical systems? Are you passionate about providing real impact to the country's toughest national security problems? If so, we're looking for someone like you to join our team at APL. The Miniature Device Technologies Group develops highly customized tools and techniques required to carry out missions around the globe. Whether it be a quick reaction need from the field or the long-term development of a novel capability, we work hand in hand with our government sponsors to conceive and realize solutions to their most challenging problems. We leverage our multi-disciplinary set of capabilities in custom application-specific integrated circuits (ASIC), printed circuit board (PCB), embedded software, field-programmable gate array (FPGA), and signal processing design to create ultra-small, low-power solutions that exceed comparable commercial alternatives. We are seeking an experienced senior physical design ASIC design engineer, to help us advance the state-of-the-art in miniature systems for a wide range of applications. In this role, you will be responsible for all back-end flow aspects, including synthesis, top-level floor-planning, timing analysis and design partitioning to meet timing requirements, SCAN and BIST insertion, and physical verification checks. You will be working closely with the ASIC design team to identify back-end issues, and assist in addressing these issues, both in the RTL and gate-level phases of the design. You will help explore process selection for new proposals and designs, assessing aspects such as achievable size and power, and availability of the necessary design features and intellectual property (IP.) Additionally, you will perform custom physical design as needed, both to complete custom block layouts, and to perform custom modifications necessary at the top level of the ASIC. As a Senior ASIC Physical Design Engineer... * Your primary responsibility will be digital back-end flow, from synthesis to a completed, verified top-level layout, ready for tapeout submission
* You will contribute to process selection for new designs and proposals
* You will floorplan the top-level layout of the digital and mixed-signal ASICs
* You will perform timing analysis and design partitioning
* You will perform SCAN and BIST insertion for maximum defect coverage
* You will work with digital designers to debug and address back-end related RTL and gate-level issues
* You will perform all physical verification, including DRC, DRC+, MCD, and LVS
* You will perform custom physical layout
* You may assist with ASIC design environment enhancements and scripting
* You will demonstrate initiative by identifying and driving process improvements, and implementing innovative solutions to complex design challenges
* You will build and maintain strong working relationships with cross-functional teams, including digital design, verification, and software teams
* You will provide leadership and guidance to junior physical design engineers, and contribute to their growth and development
* You will collaborate with the team to achieve project goals and objectives, and drive results through effective teamwork and problem-solving
* You will foster open communication and collaboration with digital designers, junior physical design engineers, and other stakeholders to ensure seamless project execution Qualifications You meet our minimum qualifications for the job if you... * Possess an Associate's degree in a technical field, or a combination of equivalent level experience/education/certifications.
* Are skilled at using Cadence ASIC design tools for back-end flow implementation
* Are skilled at using Siemens Calibre physical verification tools
* Have 6+ years of experience specifically performing back-end ASIC design
* Are able to obtain an Interim Secret level security clearance by your start date and can ultimately obtain a Secret level clearance. If selected, you will be subject to a government security clearance investigation and must meet the requirements for access to classified information. Eligibility requirements include U.S. citizenship.
You'll go above and beyond our minimum requirements if you... * Have experience with custom physical layout in Cadence Virtuoso
* Are skilled at using Siemens ASIC design tools for back-end flow implementation
* Have extensive knowledge and experience in ASIC technology characterization for process selection
* Hold an active clearance and/or have successfully undergone single-scope background investigations in the past.
#LI-AG1 About Us Why Work at APL? The Johns Hopkins University Applied Physics Laboratory (APL) brings world-class expertise to our nation's most critical defense, security, space and science challenges. While we are dedicated to solving complex challenges and pioneering new technologies, what makes us truly outstanding is our culture. We offer a vibrant, welcoming atmosphere where you can bring your authentic self to work, continue to grow, and build strong connections with inspiring teammates. At APL, we celebrate our differences of perspectives and encourage creativity and bold, new ideas. Our employees enjoy generous benefits, including a robust education assistance program, unparalleled retirement contributions, and a healthy work/life balance. APL's campus is located in the Baltimore-Washington metro area. Learn more about our career opportunities at https://www.jhuapl.edu/careers. All qualified applicants will receive consideration for employment without regard to race, creed, color, religion, sex, gender identity or expression, sexual orientation, national origin, age, physical or mental disability, genetic information, veteran status, occupation, marital or familial status, political opinion, personal appearance, or any other characteristic protected by applicable law. APL is committed to providing reasonable accommodation to individuals of all abilities, including those with disabilities. If you require a reasonable accommodation to participate in any part of the hiring process, please contact . The referenced pay range is based on JHU APL's good faith belief at the time of posting. Actual compensation may vary based on factors such as geographic location, work experience, market conditions, education/training and skill level with consideration for internal parity. For salaried employees scheduled to work less than 40 hours per week, annual salary will be prorated based on the number of hours worked. APL may offer bonuses or other forms of compensation per internal policy and/or contractual designation. Additional compensation may be provided in the form of a sign-on bonus, relocation benefits, locality allowance or discretionary payments for exceptional performance. APL provides eligible staff with a comprehensive benefits package including retirement plans, paid time off, medical, dental, vision, life insurance, short-term disability, long-term disability, flexible spending accounts, education assistance, and training and development. Applications are accepted on a rolling basis. Minimum Rate $105,000 Annually Maximum Rate $290,000 Annually

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