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Asic Manager Jobs in California (NOW HIRING)

Ayar Labs

Sr. Staff Engineer, ASIC Design

San Jose, CA · On-site

$170K - $223K/yr

Sr. Staff Engineer, ASIC Design Location: San Jose (on-site) Ayar Labs is shattering AI data ... manage his or her own time to take projects to completion with limited supervision and guidance.

Ayar Labs

Sr. Staff Engineer, ASIC Design

San Jose, CA · On-site

$180K - $223K/yr

Sr. Staff Engineer, ASIC Design Location: San Jose (on-site) Ayar Labs is shattering AI data ... manage his or her own time to take projects to completion with limited supervision and guidance.

Ayar Labs

Sr. Staff Engineer, ASIC Design

San Jose, CA

$170K - $223K/yr

Sr. Staff Engineer, ASIC Design Location: San Jose (on-site) Ayar Labs is shattering AI data ... manage his or her own time to take projects to completion with limited supervision and guidance.

Meta

Technical Program Manager, ASIC

Menlo Park, CA

$168K/yr

Technical Program Manager, ASIC Responsibilities: * Manage cross-functional infrastructure programs in a matrix organization covering a range of functional areas in Silicon Engineering, Platform ...

Eridu AI

RTL Engineer, Networking ASIC

Saratoga, CA · On-site

$210K - $275K/yr

Implement designs on ASIC platforms, ensuring compliance with industry standards and performance ... Recruiting agencies are expressly instructed not to contact hiring managers, employees, or ...

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Asic Manager information

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How much do asic manager jobs pay per hour?

As of Aug 22, 2026, the average hourly pay for asic manager in California is $24.00, according to ZipRecruiter salary data. Most workers in this role earn between $16.83 and $28.94 per hour, depending on experience, location, and employer.

What is an ASIC manager?

An ASIC Manager is a professional responsible for overseeing the design, development, and implementation of Application-Specific Integrated Circuits (ASICs). They coordinate teams of engineers, manage project timelines, and ensure that ASIC projects meet technical and business requirements. ASIC Managers often collaborate with other departments, handle resource allocation, and address technical challenges throughout the development process. Their role is crucial in industries like electronics, telecommunications, and computing, where custom hardware solutions are needed for optimized performance.

What are the key skills and qualifications needed to thrive as an ASIC manager?

To thrive as an ASIC Manager, you need deep expertise in digital and analog integrated circuit design, project management experience, and typically a degree in electrical engineering or a related field. Familiarity with EDA tools like Cadence, Synopsys, and Mentor Graphics, as well as knowledge of verification methodologies and relevant industry certifications, is crucial. Strong leadership, problem-solving abilities, and excellent communication skills help in managing cross-functional teams and collaborating with stakeholders. These skills ensure successful delivery of complex ASIC projects, meeting quality, timeline, and budget requirements.

What are the most common challenges ASIC managers face when leading design teams, and how can they address them?

ASIC Managers often encounter challenges such as balancing project timelines with technical complexities, coordinating cross-functional teams, and ensuring effective communication between design, verification, and testing groups. Managing evolving project requirements while maintaining quality standards can also be demanding. Success in this role typically relies on proactive project management, clear delegation of tasks, and fostering a collaborative team environment. Leveraging agile methodologies and regular check-ins can help address these challenges and keep projects on track.

What is the difference between Asic Manager vs Asic Engineer?

AspectAsic ManagerAsic Engineer
ResponsibilitiesOversees ASIC design projects, manages teams, coordinates with stakeholdersDesigns, develops, and tests ASIC chips
Required SkillsLeadership, project management, ASIC design knowledgeHardware description languages, circuit design, verification
CertificationsTypically none required, but PMP or management certifications helpfulASIC design certifications or relevant technical training
Work EnvironmentOffice-based, team management, project coordinationDesign labs, engineering teams, hardware development

The main difference between an Asic Manager and an Asic Engineer lies in their roles. The Asic Manager oversees projects and manages teams, focusing on coordination and leadership. In contrast, the Asic Engineer is hands-on, involved in designing and testing ASIC chips. Both roles require technical ASIC knowledge, but the Manager emphasizes leadership and project oversight, while the Engineer concentrates on technical design work.

What are the most commonly searched types of Asic jobs in California?

The most popular types of Asic jobs in California are:

What are popular job titles related to Asic Manager jobs in California?

For Asic Manager jobs in California, the most frequently searched job titles are:

What job categories do people searching Asic Manager jobs in California look for?

The top searched job categories for Asic Manager jobs in California are:

What cities in California are hiring for Asic Manager jobs?

Cities in California with the most Asic Manager job openings:

Asic Manager jobs near you
Infographic showing various Asic Manager job openings in California as of August 2026, with employment types broken down into 90% Full Time, 9% Part Time, and 1% Contract. Highlights an 81% Physical, 2% Hybrid, and 17% Remote job distribution, with an average salary of $49,928 per year, or $24 per hour.

Sr. Staff Engineer, ASIC Design

Ayar Labs

San Jose, CA • On-site

$170K - $223K/yr

Full-time

Re-posted 9 days ago

Job description

Sr. Staff Engineer, ASIC Design
Location: San Jose (on-site)
Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models. Backed by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures.

The ASIC Sr. Staff Engineer is responsible for the design, bring-up, and debug of complex digital subsystems within an electro-optical digital SoC. You will work in a dynamic startup environment as part of a small IC design team, with each team member expected to contribute across a broad range of tasks while gaining new skill sets to grow with the company.
The ideal candidate is a hands-on self-starter who can craft specifications based on input from colleagues, customers, and industry and who can effectively manage his or her own time to take projects to completion with limited supervision and guidance.
KEY RESPONSIBILITIES:
  • Develop detailed digital algorithm specifications in collaboration with analog, photonics, and firmware engineers
  • Develop and optimize RTL in verilog for use in complex electro-optical ASICs
  • Develop models and testbenches for digital and mixed-signal blocks
  • Create clear documentation of their designs to enable backend ASIC engineers to perform physical implementation (clocks and timing constraints, floorplan guidance, testability) and collaborate to ensure timing signoff
  • Bringup, evaluation, and debug of in-house custom silicon using python scripting, firmware, and control systems
  • Contribute to automated design methodologies and flows for ASIC digital design
  • Hands-on work with high-speed interconnects and optical systems
Required Qualifications:
  • BS in Electrical Engineering, Computer Engineering, or related fields
  • 5+ years of work or academic experience in ASIC design
  • History of assuming responsibility for a variety of technical tasks and completing projects independently
  • Mastery of Verilog and SystemVerilog for both RTL design and verification
  • Proficient in ASIC verification (XCelium, VCS, Questa) tools
  • Proficient in low-level programming languages (C, C++)
  • Proficient in Python
  • Working knowledge of digital timing constraints and ASIC tool flows
  • Experience working on digital designs with multiple clock domains and clock dividers
  • Experience with SOC interconnect fabrics (AMBA AXI/AHB/APB)

Preferred Qualifications:
  • MS in Electrical Engineering, Computer Engineering, or related fields
  • Proficient in ASIC synthesis (Genus, Design Compiler) tools
  • Proficient in writing timing constraints and deep understanding of timing analysis
  • Working knowledge integrating custom blocks in a digital-top flow (LEF, lib, etc.)
  • Performed silicon bring-up, debug, and evaluation
  • Working knowledge of FPGAs and/or microcontroller platforms
  • Working knowledge of the Cadence Virtuoso design environment, schematic entry, layout, and simulation
  • Experience with DFT methodologies and flows such as scan insertion, BIST, ATPG, etc
  • Knowledge of high-speed SerDes or SerDes components
  • Some knowledge of optics and control systems
Salary Range: $180,000 - $223,000
NOTE TO RECRUITERS:
Principals only. We are not accepting resumes from recruiters for this position. Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties. Please don’t send candidates to Ayar Labs, and do not contact our managers.

Ayar Labs is an Equal Opportunity Employer and is strongly committed to all policies which will afford equal opportunity employment to all qualified persons without regard to age, sex, national origin, race, color, ethnicity, creed, religion, gender identity, sexual orientation, disability, veteran status, or any other characteristic protected by law. It is the policy of Ayar Labs to provide reasonable accommodation when requested by a qualified applicant or employee with a disability, unless such accommodation would cause an undue hardship. Veterans are more than welcome and encouraged to apply.

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