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Asic Layout Design Engineer Jobs (NOW HIRING)

Fermilab

Jr. ASIC Design Engineer

Batavia, IL · On-site

$70.80K - $93.20K/yr

We are looking for a Junior ASIC Design Engineer to lead and contribute to research activities and ... Designing circuit networks using schematic entry and layout tools with full custom or timing-driven ...

Nvidia

OR · Hybrid

You'll work cross functionally with ASIC and mixed-signal engineers to customize designs for integration in VLSI products. * Take part in floor planning, custom layout and verifying against design ...

Nvidia

OR · Hybrid

You'll work cross functionally with ASIC and mixed-signal engineers to customize designs for integration in VLSI products. * Take part in floor planning, custom layout and verifying against design ...

Nvidia

Senior Mask Design Engineer

Santa Clara, CA · Hybrid

$122.10K - $164.40K/yr

You'll work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products. * Job duties will include floor planning, custom layout and verifying against design rules and ...

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Asic Layout Design Engineer information

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$45K

$120.8K

$185.5K

How much do asic layout design engineer jobs pay per year?

As of Jun 1, 2026, the average yearly pay for asic layout design engineer in the United States is $120,849.00, according to ZipRecruiter salary data. Most workers in this role earn between $90,000.00 and $144,000.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as an ASIC Layout Design Engineer, and why are they important?

To thrive as an ASIC Layout Design Engineer, you need expertise in semiconductor physics, VLSI design, and layout methodologies, typically supported by a degree in electrical engineering or a related field. Proficiency with EDA tools such as Cadence Virtuoso, Mentor Graphics, and knowledge of process design kits (PDKs) are routinely required. Attention to detail, strong problem-solving abilities, and effective collaboration skills help engineers excel in this role. These skills are crucial for ensuring accurate, efficient, and manufacturable chip designs that meet performance and reliability standards.

What are some common challenges faced by ASIC Layout Design Engineers in managing complex projects?

ASIC Layout Design Engineers often face challenges such as meeting tight design schedules, ensuring design rule compliance, and minimizing layout-induced circuit issues like parasitics and crosstalk. Balancing these technical demands with iterative feedback from verification and design teams requires effective communication and strong problem-solving skills. Additionally, staying updated with evolving EDA tools and process technologies is essential for delivering high-quality layouts within project constraints.

What are ASIC Layout Design Engineers?

ASIC Layout Design Engineers are specialized professionals who create the physical design of Application-Specific Integrated Circuits (ASICs). They translate circuit schematics into geometric representations that can be fabricated onto silicon chips, ensuring performance, power, and area specifications are met. Their work involves using electronic design automation (EDA) tools to place and route circuit elements while adhering to manufacturing constraints and design rules. They collaborate closely with circuit designers and verification engineers throughout the chip design process.

What is the difference between Asic Layout Design Engineer vs Digital IC Design Engineer?

AspectAsic Layout Design EngineerDigital IC Design Engineer
Primary FocusPhysical layout and placement of ASIC componentsLogical design and architecture of digital circuits
Skills RequiredEDA tools, layout optimization, fabrication process knowledgeHDL coding, simulation, digital logic design
Work EnvironmentASIC design teams, fabrication facilitiesDesign houses, semiconductor companies
CertificationsTypically none specific, but familiarity with industry standardsHDL certifications, digital design courses

While both roles are integral to ASIC development, the Asic Layout Design Engineer focuses on the physical implementation of circuits, ensuring manufacturability and performance. In contrast, the Digital IC Design Engineer concentrates on the logical design and verification of digital circuits. Both roles require knowledge of digital design principles, but their daily tasks and skill sets differ significantly.

More about Asic Layout Design Engineer jobs
What states have the most Asic Layout Design Engineer jobs? States with the most job openings for Asic Layout Design Engineer jobs include:
What job categories do people searching Asic Layout Design Engineer jobs look for? The top searched job categories for Asic Layout Design Engineer jobs are:
Asic Layout Design Engineer jobs near you
Infographic showing various Asic Layout Design Engineer job openings in the United States as of May 2026, with employment types broken down into 86% Full Time, and 14% Contract. Highlights an 100% In-person job distribution, with an average salary of $120,849 per year, or $58.1 per hour.
Principal Layout Design Engineer

Principal Layout Design Engineer

Ampere Computing LLC

Durham, NC • On-site

$182K - $273K/yr

Full-time

Medical, Dental, Vision, Retirement

Posted 4 days ago

Job description

Description
Invent the future with us.
Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient AI compute.
As a pioneer in the new frontier of energy efficient high-performance computing, Ampere is part of the Softbank Group of companies driving sustainable computing for AI, Cloud, and edge applications.
Join us at Ampere and work alongside a passionate and growing team - we'd love to have you apply!
About the role:
As a key member of the layout team, you will be responsible for delivering clean layouts that meet LVS, DRC, ERC, EM, and IR requirements.
Your role will involve close collaboration with various teams to ensure seamless full-chip integration and high-quality design implementation.
What you'll achieve:
  • Collaborate with the Place & Route (P&R) team to resolve full-chip integration issues.
  • Develop and improve methodologies to simplify custom macro integration into the P&R flow.
  • Floorplan and build out cells, blocks, and macros efficiently.
  • Understand, create, and debug LEF files to support design processes.
  • Design complex layouts for both analog and digital circuits using deep submicron technologies.
  • Analyze and interpret LVS, DRC, ERC, EM, and IR results to identify and resolve issues.
  • Identify schematic or layout problems and work closely with engineering teams to address them.
  • Ability to work on multiple projects across different technologies simultaneously.
  • Learn and effectively utilize Ampere's in-house design tools.
  • Coordinate with circuit engineers located in different regions and time zones.
  • Support and assist during tapeout phases to ensure successful project completion.
  • Contribute ideas as an integral part of a small, collaborative team.
  • Coach and train junior engineers to foster skill development within the team.

About you:
  • Minimum of 8 years' experience in custom layout design.
  • Current hands-on experience with 3nm technology is essential.
  • High proficiency in laying out custom digital components such as SRAM, register files, and standard cells.
  • Strong skills in designing custom analog blocks including amplifiers and resistor ladders.
  • Expertise in laying out and balancing custom clock H-trees for full-chip designs.
  • Experience with full-chip integration of custom IP alongside P&R teams.
  • Solid knowledge of Design for Manufacturability (DFM), hierarchical layout techniques, device matching, and low-parasitic layout practices.
  • Good understanding of Electromigration (EM) and IR drop analysis.
  • Proficient with Cadence XL/GXL/EXL and Mentor Graphics Calibre tools.
  • Familiarity with Cadence Innovus is a plus.
  • Experience with Totem tools for EM/IR analysis is advantageous.
  • Programming skills are a plus but not required.
  • Excellent communication skills with the ability to collaborate effectively across multiple locations and time zones.
  • Bachelor's degree & 8 years of related experience; or master's degree & 6 years; or PhD & 3 years

What we'll offer:
At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, cash long-term incentive, and comprehensive benefits.
The full base pay range for this role is between $182,000 and $273,000, except in the San Francisco Bay Area where the range is between $195,000 and $292,000.
Our benefits include health, wellness, and financial programs that support employees through every stage of life.
Benefit highlights include:
  • Premium medical insurance, dental insurance, vision insurance, as well as income protection and a 401K retirement plan, so that you can feel secure in your health and financial future.
  • Unlimited Flextime and 10+ paid holidays so that you can embrace a healthy work-life balance.
  • A variety of healthy snacks, energizing espresso, and refreshing drinks to keep you fueled and focused throughout the day.

And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are excited to share more about our career opportunities with you through the interview process.
#LI-TC
#LI-Hybrid
Ampere is an inclusive and equal opportunity employer and welcomes applicants from all backgrounds. All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, religion, age, veteran and/or military status, sex, sexual orientation, gender, gender identity, gender expression, physical or mental disability, or any other basis protected by federal, state or local law.

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