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Asic Fpga Design Jobs (NOW HIRING)

Lockheed Martin

ASIC & FPGA Design Engineer Sr

Orlando, FL

$114K - $158K/yr

You will be the Senior ASIC & FPGA Design Engineer for the Command Launch Assembly (CLA) FPGA team within Missiles&Fire Control (MFC). Our team delivers the digital heart beat that powers the Next ...

Lockheed Martin Corporation

$123K - $169K/yr

As an ASIC & FPGA Associate Engineering Manager , you will lead and manage a team of ASIC/FPGA design and verification engineers in executing design services for programs in the integration and test ...

Lockheed Martin

ASIC/FPGA Design Engineer IV

Littleton, CO · On-site

$124K - $171K/yr

Join Our Team as an ASIC & FPGA Design Engineer where you will support over 50 different programs and research and development (R&D) efforts, affecting technology across military space, civil space ...

Lockheed Martin

ASIC & FPGA Design Engineer Sr.

Orlando, FL · On-site

$114K - $158K/yr

You will be the Senior ASIC & FPGA Design Engineer for the Programmable Logic Design team supporting the Next Generation Short Range Interceptor (NGSRI). Our team creates the digital heart beats ...

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Asic Fpga Design information

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$70K

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$210.5K

How much do asic fpga design jobs pay per year?

As of Jun 12, 2026, the average yearly pay for asic fpga design in the United States is $147,056.00, according to ZipRecruiter salary data. Most workers in this role earn between $123,000.00 and $169,500.00 per year, depending on experience, location, and employer.

How much do ASIC FPGA make?

Salaries for ASIC FPGA design engineers typically range from $80,000 to $150,000 annually, depending on experience, location, and company size. Senior roles or those with specialized skills in FPGA development and hardware description languages can earn higher compensation, often exceeding $180,000 per year.

Is ASIC design in demand?

ASIC FPGA design is in high demand due to the increasing need for custom hardware solutions in industries like telecommunications, automotive, and data centers. Professionals with skills in hardware description languages such as VHDL or Verilog, and experience with FPGA development tools, are particularly sought after as companies focus on optimizing performance and power efficiency.

Is FPGA going to be replaced by AI?

As an FPGA design engineer, it is unlikely that FPGAs will be fully replaced by AI, as FPGAs provide customizable hardware acceleration that AI algorithms often require. AI can complement FPGA development by optimizing designs or automating certain tasks, but FPGAs remain essential for applications needing low latency, high throughput, and hardware-level flexibility. Both skills in FPGA architecture and AI integration are valuable in the evolving tech landscape.

What is the difference between Asic Fpga Design vs FPGA Design Engineer?

AspectAsic Fpga DesignFPGA Design Engineer
CredentialsBS/MS in Electrical Engineering or Computer Engineering, certifications like FPGA or ASIC design coursesSimilar educational background, often with certifications in FPGA design
Work EnvironmentDesigning integrated circuits for ASICs and FPGAs, often in semiconductor or electronics companiesDeveloping FPGA-based solutions, typically in electronics or embedded systems firms
Industry UsageUsed in high-volume chip manufacturing, custom hardware solutionsUsed in prototyping, embedded systems, and custom hardware projects

Asic Fpga Design focuses on designing both ASICs and FPGAs, often involving complex chip architecture, while FPGA Design Engineers primarily develop FPGA-based solutions for various applications. Both roles require similar skills and certifications but differ in scope and application focus.

What engineer makes $500,000 a year?

In the field of ASIC FPGA design, senior engineers with extensive experience, specialized skills in hardware description languages, and certifications can earn salaries approaching or exceeding $500,000 annually, especially in high-cost living areas or within large tech companies. Such compensation often includes bonuses, stock options, and other benefits for top-tier professionals in the industry.
What cities are hiring for Asic Fpga Design jobs? Cities with the most Asic Fpga Design job openings:
ASIC/FPGA Design Engineer (SMES)

ASIC/FPGA Design Engineer (SMES)

L3Harris Technologies

Camden, NJ • On-site

$111K - $151K/yr

Full-time

Medical, Retirement, PTO

Posted 27 days ago

Job description

L3Harris is dedicated to recruiting and developing high-performing talent who are passionate about what they do. Our employees are unified in a shared dedication to our customers' mission and quest for professional growth. L3Harris provides an inclusive, engaging environment designed to empower employees and promote work-life success. Fundamental to our culture is an unwavering focus on values, dedication to our communities, and commitment to excellence in everything we do.

L3Harris is the Trusted Disruptor in defense tech. With customers' mission-critical needs always in mind, our employees deliver end-to-end technology solutions connecting the space, air, land, sea and cyber domains in the interest of national security.

Job Title: ASIC/FPGA Design Engineer (SMES)

Job Code: 34234

Job Location: Camden, NJ

Schedule: 9/80 Regular with every other Friday off

Are you ready to take your engineering career to the next level and be a part of something truly extraordinary? Join our trailblazing team in the Philadelphia metro area, where you'll dive into the thrilling world of high-assurance encryption products and programs that are pivotal to national defense. Our rapidly expanding business is not just growing-it's exploding with opportunities for innovation and impact in network and tactical encryption products and systems. Imagine working on the front lines of technology, developing state-of-the-art solutions that safeguard our nation's security. You'll collaborate with some of the brightest minds in the industry, in an environment that champions creativity and excellence. If you're passionate about tackling complex challenges and eager to contribute to groundbreaking projects that make a real difference to our warfighters, citizens, and nation; this is your chance to shine. Apply now and embark on this exhilarating journey with us, shaping the future of defense technology!

Eligible candidates with an active government issued clearance upon the time of hire will receive a sign-on payment in the amount of$ 15,000.

Job Description:

Reporting to the Manager, Engineering (ASIC/FPGA), the Senior Member of Engineering Staff (SMES) will be part of the key ASIC/FPGA design team, responsible for the delivery of FPGA/ASICs for high-speed crypto applications. S/he will architect, implement high speed crypto architectures, on ASICs/Xilinx Zynq/MPSOC class FPGAs, with hands on design/debug with Ethernet, TCP/IP protocols.

L3Harris has state-of-the-art EDA flows/methodologies including Synopsys DC/Primetime/Synplify, Xilinx/Intel/Microchip EDA with HLS, Mentor EDA Family suite : Questa, VIPs, UVM framework, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), Questa Lint, and Catapult (HLS). This is a key, high impact role in the organization to ensure robust quality and delivery of communication products for National Security.

Essential Functions:

  • Responsible for deriving engineering specifications from system requirements and developing detailed architecture
  • Execute design (RTL AND/OR HLS (C++ to RTL)) and RTL quality (RDC, CDC, Formal, Lint)
  • Generate test plans
  • Perform module level verification, synthesis/STA, Lab debug, SW driven validation on Linux based SOC evaluation boards
  • Silicon/FPGA bring up, characterization and production ramp/support/collateral

Qualifications:

  • BSEE, MSEE Preferred.
  • 5+ year's equivalent experience developing, implementing, and verification of high-performance communications/networking ASIC/FPGA products.
  • Experience mapping algorithms and standards (Ethernet, TCP/IP, AXI) to hardware and architecture/system design tradeoffs.
  • Proficient with CDC, RDC. Formal EDA.
  • Proficient in VHDL.
  • Proficient with Synthesis/PAR: SDC, Synopsys Synplify, Vivado
  • Strong logic/board debug, and analytical skills.
  • Experience with project leadership and EVM
  • Excellent written, verbal, and presentation skills.
  • Active SECRET Clearance

Preferred Additional Skills:

  • A big plus if the candidate possesses "any" of the following:
  • Proficiency in C++ (OOP)
  • Proficiency with Xilinx MPSOC design with writing/debugging with SDKs, BSPs on bare metal/PetaLinux OS.
  • Knowledge of PCIe, NVMe, USB protocols.
  • Experience with High level synthesis (Xilinx Vivado HLS, AND/OR Mentor Calypto ).

In compliance with pay transparency requirements, the salary range for this role is $111,515 - $151,500. This is not a guarantee of compensation or salary, as final offer amount may vary based on factors including but not limited to experience and geographic location. L3Harris also offers a variety of benefits, including health and disability insurance, 401(k) match, flexible spending accounts, EAP, education assistance, parental leave, paid time off, and company-paid holidays. The specific programs and options available to an employee may vary depending on date of hire, schedule type, and the applicability of collective bargaining agreements.

L3Harris Technologies is proud to be an Equal Opportunity Employer. L3Harris is committed to treating all employees and applicants for employment with respect and dignity and maintaining a workplace that is free from unlawful discrimination. All applicants will be considered for employment without regard to race, color, religion, age, national origin, ancestry, ethnicity, gender (including pregnancy, childbirth, breastfeeding or other related medical conditions), gender identity, gender expression, sexual orientation, marital status, veteran status, disability, genetic information, citizenship status, characteristic or membership in any other group protected by federal, state or local laws. L3Harris maintains a drug-free workplace and performs pre-employment substance abuse testing and background checks, where permitted by law.

Please be aware many of our positions require the ability to obtain a security clearance. Security clearances may only be granted to U.S. citizens. In addition, applicants who accept a conditional offer of employment may be subject to government security investigation(s) and must meet eligibility requirements for access to classified information.

By submitting your resume for this position, you understand and agree that L3Harris Technologies may share your resume, as well as any other related personal information or documentation you provide, with its subsidiaries and affiliated companies for the purpose of considering you for other available positions.

L3Harris Technologies is an E-Verify Employer. Please click here for the E-Verify Poster in English or Spanish. For information regarding your Right To Work, please click here for English or Spanish.

Employment Type: Full-Time

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