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Asic Development Engineer Jobs in Texas (NOW HIRING)

Nvidia

Senior ASIC Verification Engineer

Austin, TX · Hybrid

NVIDIA is seeking an outstanding Senior ASIC Verification Engineer to verify the design and ... Define the verification scope, and contribute to the development of the verification infrastructure ...

Nvidia

Senior ASIC Verification Engineer

Austin, TX · Hybrid

The NVIDIA Clocks Team is looking for an excellent Senior ASIC Verification engineer with extensive ... development, automation, validation flows development, coverage metrics, test execution, bug ...

Cisco

ASIC DFx & Test Architect Lead

Austin, TX · On-site

$210K - $305K/yr

Bachelor's on Electrical Engineering with 10+ years (or Master's with 8+ years) of experience on ASIC hardware development * Prior experience with ASIC DFx and test relevant standards, and techniques.

SpaceX

Sr. ASIC DFT Engineer (Silicon)

Austin, TX · On-site

SR. ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... development and debug * Experience collaborating with cross-functional teams (e.g., design ...

Meta

ASIC Engineer, Physical Design

Austin, TX

$114K/yr

As an ASIC Engineer focused on Physical Design, you will drive the physical implementation of ... Contribute to the development and documentation of physical design flows, best practices, and ...

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Asic Development Engineer information

What engineer makes $500,000 a year?

An experienced ASIC Development Engineer working in high-demand sectors such as semiconductor design or advanced chip development can earn $500,000 or more annually, especially with seniority, specialized skills, and in competitive markets. Compensation often includes base salary, bonuses, and stock options, particularly in large tech or semiconductor companies.

What is the difference between Asic Development Engineer vs FPGA Design Engineer?

AspectAsic Development EngineerFPGA Design Engineer
Required CredentialsBachelor's or Master's in Electrical Engineering, VLSI, or related fields; knowledge of ASIC design toolsBachelor's or Master's in Electrical Engineering, Digital Design; familiarity with FPGA development tools
Work EnvironmentDesigning and verifying custom silicon chips in semiconductor labs or R&D centersDeveloping and testing FPGA-based solutions in hardware labs or embedded systems environments
Industry UsageUsed in semiconductor companies, integrated circuit design firms, and tech giantsCommon in telecommunications, aerospace, and embedded systems industries

While both roles involve digital hardware design, Asic Development Engineers focus on creating custom chips for high-performance applications, whereas FPGA Design Engineers work on programmable hardware solutions. Both require strong digital design skills and familiarity with hardware description languages, but their end products and development environments differ.

What engineers make $300,000 a year?

Senior engineers in high-demand fields such as software engineering, data engineering, and ASIC development can earn $300,000 or more annually, especially with extensive experience, specialized skills, and working in competitive industries or companies. Roles like senior hardware or ASIC design engineers often reach this level with advanced technical expertise and leadership responsibilities.

Are ASIC engineers in demand?

ASIC development engineers are in high demand due to the growth of industries like consumer electronics, telecommunications, and automotive systems that require custom integrated circuits. Skills in hardware description languages such as VHDL or Verilog, along with experience in FPGA prototyping and verification, enhance employability in this field.

How much do ASIC engineers make?

ASIC development engineers typically earn between $80,000 and $150,000 annually, depending on experience, location, and company size. Senior engineers with specialized skills in hardware description languages and verification tools can earn higher salaries, often exceeding $150,000.
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Asic Development Engineer jobs near you
Senior Staff ASIC CAD Flow Infrastructure Engineer

Senior Staff ASIC CAD Flow Infrastructure Engineer

Marvell

Austin, TX • On-site

Full-time

Life, Retirement

Posted 5 days ago

Job description

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

We are seeking a highly motivated and technically strong ASIC CAD Flow & Infrastructure Engineer to drive the development, deployment, and support of next-generation ASIC design infrastructure. This role is responsible for defining scalable EDA methodologies, automation frameworks, and design flows that enable efficient development of complex SoCs across multiple product generations.
The ideal candidate combines deep semiconductor design-flow knowledge with software engineering expertise. The individual will collaborate closely with Design, Physical Design and IT teams to deliver robust, high-performance CAD solutions that improve engineering productivity and design quality.

What You Can Expect

  • Develop and maintain CAD frameworks using Python, Tcl, Shell, and modern software engineering practices

  • Build flow orchestration systems, dashboards, analytics, and monitoring tools

  • Developed and maintained automation frameworks for integrating standard-cell libraries, memory macros, and IP blocks across multiple ASIC design and implementation flow entry points

  • Establish best practices for synthesis and physical implementation

  • Develop standardized flow frameworks that maximize reusability, maintainability, and automation

What We're Looking For

  • Bachelor's degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience or Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience or equivalent professional experience in lieu of a formal degree

  • At least 5+ years of experience in ASIC CAD, EDA, design methodology, or infrastructure engineering. 8+ years prferred.

  • Strong understanding of ASIC/SoC development lifecycle from RTL through tapeout

  • Proficiency in Python and Tcl scripting

  • Experience with Linux-based development environments

  • Experience supporting commercial EDA tools from Synopsys, Cadence, Siemens EDA, or equivalent

  • Familiarity with data analytics, telemetry, and AI-assisted design methodologies

  • Strong cross-functional leadership and communication skills

Expected Base Pay Range (USD)

129,100 - 191,030, $ per annum

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life's most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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