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Asic Development Engineer Jobs in Carrollton, TX

Purple Hires Inc

ASIC DFT Engineer

Plano, TX · Remote

Lead ASIC DFT Engineer Location: Remote, (Onsite) Duration: Contract Year of Exp: 8+ yrs to 15 yrs ... Experience working across multiple ASIC technology nodes and complex product development cycles.

Purple Hires Inc

ASIC Engineer - Remote

Plano, TX · Remote

Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and ... Experience working across multiple ASIC technology nodes and complex product development cycles.

Purple Hires Inc

Lead ASIC DFT Engineer

Plano, TX · Remote

Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and ... Experience working across multiple ASIC technology nodes and complex product development cycles.

Prattwhitney

Senior ASIC/FPGA Design Engineer

Mckinney, TX · On-site

$86.80 - $165.20/hr

We bring the strength of more than 100 years of experience and renowned engineering expertise to ... Experience with ASIC design and development processes * Experience with System Verilog and UVM ...

Raytheon

Senior ASIC/FPGA Design Engineer

Mckinney, TX

$114K - $157K/yr

We bring the strength of more than 100 years of experience and renowned engineering expertise to ... Experience with ASIC design and development processes * Experience with System Verilog and UVM ...

Raytheon

Senior ASIC/FPGA Design Engineer

Mckinney, TX

$114K - $157K/yr

We bring the strength of more than 100 years of experience and renowned engineering expertise to ... Experience with ASIC design and development processes * Experience with System Verilog and UVM ...

Purple Hires Inc

DFT Engineer

Plano, TX · Remote

Lead ASIC DFT Engineer Location: Remote, (Onsite) Duration: Contract Year of Exp: 8+ yrs to 15 yrs ... Experience working across multiple ASIC technology nodes and complex product development cycles.

Raytheon

FPGA Engineer II

Plano, TX

$124K - $159K/yr

In this role as an FPGA Engineer II , you will be supporting a development program within the ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)

Raytheon Technologies

FPGA Engineer II

Plano, TX · On-site

$117K - $162K/yr

In this role as an FPGA Engineer II , you will be supporting a development program within the ... FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)

Raytheon

Principal FPGA Engineer

Mckinney, TX

$129K - $157K/yr

FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (System Verilog coding ... Proposal development experience. * Experience with intellectual property generation (patents ...

Raytheon Technologies

Principal FPGA Engineer

Mckinney, TX · On-site

$129K - $157K/yr

FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (System Verilog coding ... Proposal development experience. * Experience with intellectual property generation (patents ...

Raytheon

Principal FPGA Engineer

Mckinney, TX

$129K - $157K/yr

FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (System Verilog coding ... Proposal development experience. * Experience with intellectual property generation (patents ...

Purple Hires Inc

Design Verification Engineer

Plano, TX · On-site

$130K - $158K/yr

and other details - We are seeking an ASIC Design Verification Engineer whose role will be to ... Experience with test planning, testbench development, constrained-random testing, and coverage ...

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All JobsAsic Development Engineer JobsAsic Development Engineer Jobs in Carrollton, TX

Asic Development Engineer information

See Carrollton, TX salary details

$47.3K

$92.8K

$148.2K

How much do asic development engineer jobs pay per year?

As of Aug 24, 2026, the average yearly pay for asic development engineer in Carrollton, TX is $92,815.00, according to ZipRecruiter salary data. Most workers in this role earn between $76,700.00 and $102,800.00 per year, depending on experience, location, and employer.

What is the difference between Asic Development Engineer vs FPGA Design Engineer?

AspectAsic Development EngineerFPGA Design Engineer
Required CredentialsBachelor's or Master's in Electrical Engineering, VLSI, or related fields; knowledge of ASIC design toolsBachelor's or Master's in Electrical Engineering, Digital Design; familiarity with FPGA development tools
Work EnvironmentDesigning and verifying custom silicon chips in semiconductor labs or R&D centersDeveloping and testing FPGA-based solutions in hardware labs or embedded systems environments
Industry UsageUsed in semiconductor companies, integrated circuit design firms, and tech giantsCommon in telecommunications, aerospace, and embedded systems industries

While both roles involve digital hardware design, Asic Development Engineers focus on creating custom chips for high-performance applications, whereas FPGA Design Engineers work on programmable hardware solutions. Both require strong digital design skills and familiarity with hardware description languages, but their end products and development environments differ.

Are ASIC Development Engineers in demand?

ASIC Development Engineers are in high demand due to the growing need for custom hardware solutions in industries like telecommunications, consumer electronics, and automotive. Skilled engineers with knowledge of hardware description languages such as VHDL or Verilog, along with experience in FPGA and ASIC design, are particularly sought after in the technology sector.

How much do ASIC development engineers make?

ASIC development engineers typically earn between $80,000 and $150,000 annually, depending on experience, location, and company size. Senior engineers with specialized skills in hardware description languages and verification tools can earn higher salaries, often exceeding $150,000.

What does an ASIC development engineer do?

An ASIC development engineer designs, develops, and tests application-specific integrated circuits (ASICs) used in electronic devices. They work with hardware description languages like VHDL or Verilog, collaborate with cross-functional teams, and use CAD tools to create efficient chip architectures that meet performance and power specifications.

What are popular job titles related to Asic Development Engineer jobs in Carrollton, TX?

For Asic Development Engineer jobs in Carrollton, TX, the most frequently searched job titles are:

What job categories do people searching Asic Development Engineer jobs in Carrollton, TX look for?

The top searched job categories for Asic Development Engineer jobs in Carrollton, TX are:

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Cities near Carrollton, TX with the most Asic Development Engineer job openings:

Asic Development Engineer jobs near you

ASIC DFT Engineer

Plano, TX • Remote

Purple Hires Inc
See more jobs at Purple Hires Incexternal

Contractor

Re-posted 29 days ago

Job description

Role: Lead ASIC DFT Engineer
Location: Remote, (Onsite)
Duration: Contract
Year of Exp: 8+ yrs to 15 yrs.
Job Description:
We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues. The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield.
Key Responsibilities:
  • Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
  • Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high coverage and robust testability.
  • Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up phases.
  • Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon issues.
  • Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis.
  • Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation issues.
  • Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug.
  • Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration.
  • Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality.
  • Act as a technical escalation point for advanced DFT and post-silicon debug issues.
  • Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation.
  • Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and debug productivity.
Required Skills & Qualifications:
  • Strong hands-on experience in ASIC DFT with end-to-end ownership.
  • Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
  • Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
  • Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
  • Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
  • Experience with MBIST implementation and verification; SMS experience preferred.
  • Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
  • Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
  • Proven post-silicon debug and silicon bring-up experience.
  • Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
  • Strong communication skills and the ability to work independently with minimal ramp-up.
Preferred Experience:
  • MBIST post-silicon validation.
  • ATPG simulations and fault coverage debug.
  • DFT RTL, DFD, DFT verification, and IP-level DFT integration.
  • DFT SDC creation and DFT timing closure support.
  • Boundary scan, iJTAG, SSN, and design-for-debug methodologies.
  • TCL/PERL scripting for DFT automation, reporting, and debug.
  • Experience working across multiple ASIC technology nodes and complex product development cycles.
  • Familiarity with yield learning, diagnosis, and manufacturing test optimization.