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Asic Design Manager Jobs in Oregon (NOW HIRING)

K2 Space

Principal ASIC Physical Design Engineer

OR · On-site +1

$190K - $280K/yr

This role also involves managing external physical design partners, driving tool and flow decisions ... years of experience in ASIC physical design for high-performance SoCs. * Proven end-to-end ...

Intel

DFT Application Engineer

Hillsboro, OR · On-site

Self-driven and results-oriented with ability to manage multiple complex tasks effectively ... Hands-on experience in Design Implementation and methodology (ASIC design, Fullchip Integration ...

Rambus

PE Logic Design

Hillsboro, OR · Hybrid

$127K - $236K/yr

Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA) with BSEE, or * 8+ years of logic design experience (ASIC/FPGA) with MSEE Definite Plus: * ASIC ...

Rambus

PE Logic Design

Hillsboro, OR · Hybrid

$127K - $236K/yr

Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA) with BSEE, or * 8+ years of logic design experience (ASIC/FPGA) with MSEE Definite Plus: * ASIC ...

Rambus

PE Logic Design

Hillsboro, OR · On-site

$127K - $236K/yr

Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA) with BSEE, or * 8+ years of logic design experience (ASIC/FPGA) with MSEE Definite Plus: * ASIC ...

Rambus.com

PE Logic Design

Hillsboro, OR · On-site

$150 - $200/hr

Solid communication and project management skills * 10+ years of logic design experience(ASIC/FPGA)with BSEE, or * 8+ years of logic designexperience(ASIC/FPGA)with MSEE Definite Plus: * ASIC ...

Rambus

Hardware Design Engineer

Hillsboro, OR · Hybrid

$106K - $198K/yr

Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently * Solid communication and project management skills * 5+ years of logic design experience * BSEE ...

Rambus

Hardware Design Engineer

Hillsboro, OR · Hybrid

$106K - $198K/yr

Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently * Solid communication and project management skills * 5+ years of logic design experience * BSEE ...

Rambus

Hardware Design Engineer

Hillsboro, OR · On-site

$106K - $198K/yr

Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently * Solid communication and project management skills * 5+ years of logic design experience * BSEE ...

Rambus

Principal Logic Design Engineer

Hillsboro, OR · Hybrid

$127K - $287K/yr

Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA) with BSEE, or * 8+ years of logic design experience (ASIC/FPGA) with MSEE Definite Plus: * ASIC ...

Rambus

Principal Logic Design Engineer

Hillsboro, OR · Hybrid

$127K - $287K/yr

Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA) with BSEE, or * 8+ years of logic design experience (ASIC/FPGA) with MSEE Definite Plus: * ASIC ...

Rambus.com

Principal Logic Design Engineer

Hillsboro, OR · On-site

$150 - $200/hr

Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA) with BSEE, or * 8+ years of logic design experience (ASIC/FPGA) with MSEE Definite Plus * ASIC ...

Nvidia

Senior ASIC Timing Engineer

Hillsboro, OR · Hybrid

... management. Expertise in analysis and fixing of timing paths through ECOs including crosstalk and ... Experience in physical design and optimization e.g., synthesis, placement, routing, logic ...

Rambus

Principal Logic Design Engineer

Hillsboro, OR · On-site

$127K - $287K/yr

Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA) with BSEE, or * 8+ years of logic design experience (ASIC/FPGA) with MSEE Definite Plus: * ASIC ...

Rambus

Principal Logic Design Engineer

Hillsboro, OR · On-site

$127K - $287K/yr

Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA) with BSEE, or * 8+ years of logic design experience (ASIC/FPGA) with MSEE Definite Plus: * ASIC ...

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Showing results 21-40

All JobsAsic Design JobsAsic Design Manager JobsAsic Design Manager Jobs in Oregon

Asic Design Manager information

See Oregon salary details

$44.4K

$121K

$213K

How much do asic design manager jobs pay per year?

As of Sep 8, 2026, the average yearly pay for asic design manager in Oregon is $121,050.00, according to ZipRecruiter salary data. Most workers in this role earn between $88,300.00 and $152,200.00 per year, depending on experience, location, and employer.

What does an ASIC Design Manager do?

An ASIC Design Manager oversees the design and development of Application Specific Integrated Circuits (ASICs), managing a team of engineers through the entire chip design process. They coordinate project timelines, ensure technical specifications are met, and facilitate communication between design, verification, and manufacturing teams. Their role also involves resource planning, risk management, and ensuring that the final product meets performance, cost, and quality targets.

What are the key skills and qualifications needed to thrive as an ASIC Design Manager?

To thrive as an ASIC Design Manager, you need expertise in digital and analog ASIC design, project management experience, and typically a degree in electrical engineering or a related field. Familiarity with industry-standard EDA tools (such as Cadence or Synopsys), verification methodologies, and knowledge of relevant design flows is crucial. Strong leadership, communication, and problem-solving skills help manage teams and coordinate with cross-functional stakeholders. These competencies ensure high-quality chip designs are delivered on time and meet performance and cost targets, which is vital for organizational success.

What are some common challenges faced by an ASIC Design Manager in leading multidisciplinary teams?

ASIC Design Managers often navigate the complexities of coordinating multidisciplinary teams, including digital, analog, verification, and physical design engineers. One common challenge is ensuring clear communication across these specialties to maintain alignment on project goals, timelines, and technical requirements. Additionally, managing shifting priorities, resolving technical bottlenecks, and balancing resource allocation are frequent hurdles. Successful managers foster collaboration, set clear expectations, and leverage structured project management practices to keep teams productive and motivated.

What is the difference between Asic Design Manager vs Asic Design Engineer?

AspectAsic Design ManagerAsic Design Engineer
ResponsibilitiesOversees ASIC design projects, manages teams, and coordinates with stakeholdersPerforms ASIC design, coding, simulation, and verification tasks
Required SkillsLeadership, project management, ASIC design knowledgeHardware description languages, circuit design, verification skills
ExperienceTypically 8+ years in ASIC design, with leadership experienceUsually 2-5 years in ASIC design roles
Work EnvironmentDesign teams, project planning, cross-functional collaborationDesign labs, simulation environments, coding and testing

The main difference between an Asic Design Manager and an Asic Design Engineer lies in their roles. The manager oversees projects and teams, focusing on leadership and coordination, while the engineer concentrates on technical ASIC design and implementation. Both roles require ASIC design expertise, but the manager's role is more strategic and supervisory.

What are popular job titles related to Asic Design Manager jobs in Oregon?

For Asic Design Manager jobs in Oregon, the most frequently searched job titles are:

What job categories do people searching Asic Design Manager jobs in Oregon look for?

The top searched job categories for Asic Design Manager jobs in Oregon are:

What cities in Oregon are hiring for Asic Design Manager jobs?

Cities in Oregon with the most Asic Design Manager job openings:

Asic Design Manager jobs near you
Infographic showing various Asic Design Manager job openings in Oregon as of August 2026, with employment types broken down into 84% Full Time, 15% Part Time, and 1% Contract. Highlights an 81% Physical, 2% Hybrid, and 17% Remote job distribution, with an average salary of $121,050 per year, or $58.2 per hour.

Principal ASIC Physical Design Engineer

K2 Space

OR • On-site, Remote

$190K - $280K/yr

Full-time

Medical, Dental, Vision, Life, PTO

Re-posted 14 days ago

Job description

The Role

We are looking for a Principal ASIC Physical Design Engineer to lead the implementation of complex SoCs for next-generation satellite and space systems. You will own the full physical design flow-from RTL handoff to GDSII-and collaborate closely with architecture, RTL design, DFT, and packaging teams. This role also involves managing external physical design partners, driving tool and flow decisions, and ensuring first-pass silicon success in advanced FinFET technologies. You'll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with external partners. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will develop and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have contributed to developing cutting-edge SoCs that will fly in space. 

Responsibilities

  • Own the complete RTL-to-GDSII flow: synthesis, floorplanning, place & route, clock tree synthesis (CTS), static timing analysis (STA), physical verification (DRC/LVS), and sign-off.
  • Develop and maintain physical design methodologies, scripts, and automation to optimize performance, power, and area (PPA).
  • Collaborate with front-end and verification teams to ensure clean handoffs, timing closure, and efficient design iteration.
  • Drive timing closure across multiple voltage and process corners, including sign-off with foundry-qualified tools.
  • Partner with package, SI/PI, and test teams for package-aware floorplanning and chip-to-board integration.
  • Manage and technically guide external physical design partners and service vendors, ensuring alignment on milestones, deliverables, and quality standards.
  • Work with EDA vendors to debug and optimize tool flows, and evaluate new methodologies.
  • Support chip bring-up and debug through close collaboration with post-silicon and test teams.
  • Support your product through production and spaceflight.

Required Qualifications 

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
  • 10+ years of experience in ASIC physical design for high-performance SoCs.
  • Proven end-to-end expertise in RTL-to-GDSII flows using industry tools (Synopsys, Cadence, or Siemens).
  • Strong hands-on experience with timing closure, IR drop analysis, and ECO implementation.
  • Deep understanding of physical design constraints for multi-clock, multi-voltage, and hierarchical SoCs.
  • Experience with advanced FinFET process nodes.
  • Prior experience managing or coordinating offshore/outsourced PD teams or vendors.
  • Familiarity with DFT integration, STA sign-off, and power domain implementation (UPF/CPF).
  • Excellent communication, leadership, and cross-functional collaboration skills.
  • Act as technical leader and subject-matter expert helping to teach, grow, and mentor others in the team.

Preferred Qualifications 

  • Exposure to radiation-hardened or space-qualified ASICs.
  • Experience with chip-package co-design or advanced packaging (2.5D/3D).
  • Familiarity with physical design service vendor management or offshore collaboration.
  • Experience driving tapeouts through TSMC.
  • Experience with Gate-All-Around technologies.
  • Experience working in cross-functional, geographically distributed teams.

Compensation and Benefits:

  • Base salary range for this role is $190,000 - $280,000 + equity in the company
  • Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
  • Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks
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About K2 Space

Sourced by ZipRecruiter

Industry

Guided missile and space vehicle manufacturing

Company size

11 - 50 Employees

Headquarters location

Los Angeles, CA, US

Year founded

2022

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