DFT Application Engineer
Hillsboro, OR · On-site
Self-driven and results-oriented with ability to manage multiple complex tasks effectively ... Hands-on experience in Design Implementation and methodology (ASIC design, Fullchip Integration ...
DFT Application Engineer
Hillsboro, OR · On-site
Self-driven and results-oriented with ability to manage multiple complex tasks effectively ... Hands-on experience in Design Implementation and methodology (ASIC design, Fullchip Integration ...
Proven success managing long-cycle, highly technical, multi-stakeholder sales pursuits. * Strong ... Extensive network across the ASIC and broader semiconductor ecosystem, including IC design firms ...
Proven success managing long-cycle, highly technical, multi-stakeholder sales pursuits. * Strong ... Extensive network across the ASIC and broader semiconductor ecosystem, including IC design firms ...
Hardware Design Engineer
Hillsboro, OR · Hybrid
$106K - $198K/yr
Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently * Solid communication and project management skills * 5+ years of logic design experience * BSEE ...
Hardware Design Engineer
Hillsboro, OR · Hybrid
$106K - $198K/yr
Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently * Solid communication and project management skills * 5+ years of logic design experience * BSEE ...
Hardware Design Engineer
Hillsboro, OR · Hybrid
$106K - $198K/yr
Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently * Solid communication and project management skills * 5+ years of logic design experience * BSEE ...
Hardware Design Engineer
Hillsboro, OR · Hybrid
$106K - $198K/yr
Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently * Solid communication and project management skills * 5+ years of logic design experience * BSEE ...
Hardware Design Engineer
Hillsboro, OR · On-site
$106K - $198K/yr
Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently * Solid communication and project management skills * 5+ years of logic design experience * BSEE ...
Hardware Design Engineer
Hillsboro, OR · On-site
$106K - $198K/yr
Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently * Solid communication and project management skills * 5+ years of logic design experience * BSEE ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $236K/yr
Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA) with BSEE, or * 8+ years of logic design experience (ASIC/FPGA) with MSEE Definite Plus: * ASIC ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $236K/yr
Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA) with BSEE, or * 8+ years of logic design experience (ASIC/FPGA) with MSEE Definite Plus: * ASIC ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $236K/yr
Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA) with BSEE, or * 8+ years of logic design experience (ASIC/FPGA) with MSEE Definite Plus: * ASIC ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $236K/yr
Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA) with BSEE, or * 8+ years of logic design experience (ASIC/FPGA) with MSEE Definite Plus: * ASIC ...
FPGA Engineering Manager (MTD, Tualatin, OR)
Tualatin, OR · On-site
$155K - $248K/yr
... ASIC or FPGA design * Minimum of 5 years of experience as an FPGA/ASIC project lead, driving ... Experience as a first level manager of an engineering team. * Experience with FPGA Transceiver ...
FPGA Engineering Manager (MTD, Tualatin, OR)
Tualatin, OR · On-site
$155K - $248K/yr
... ASIC or FPGA design * Minimum of 5 years of experience as an FPGA/ASIC project lead, driving ... Experience as a first level manager of an engineering team. * Experience with FPGA Transceiver ...
Principal Logic Design Engineer
Hillsboro, OR · On-site
$127K - $236K/yr
Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA) with BSEE, or * 8+ years of logic design experience (ASIC/FPGA) with MSEE Definite Plus: * ASIC ...
Principal Logic Design Engineer
Hillsboro, OR · On-site
$127K - $236K/yr
Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA) with BSEE, or * 8+ years of logic design experience (ASIC/FPGA) with MSEE Definite Plus: * ASIC ...
Principal Logic Design Engineer
Hillsboro, OR · On-site
$127K - $236K/yr
Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA) with BSEE, or * 8+ years of logic design experience (ASIC/FPGA) with MSEE Definite Plus: * ASIC ...
Principal Logic Design Engineer
Hillsboro, OR · On-site
$127K - $236K/yr
Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA) with BSEE, or * 8+ years of logic design experience (ASIC/FPGA) with MSEE Definite Plus: * ASIC ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $236K/yr
Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA) with BSEE, or * 8+ years of logic design experience (ASIC/FPGA) with MSEE Definite Plus: * ASIC ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $236K/yr
Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA) with BSEE, or * 8+ years of logic design experience (ASIC/FPGA) with MSEE Definite Plus: * ASIC ...
... generation and management. * Expertise in analysis and fixing of timing paths through ECOs ... Experience in physical design and optimization e.g., synthesis, placement, routing, logic ...
... generation and management. * Expertise in analysis and fixing of timing paths through ECOs ... Experience in physical design and optimization e.g., synthesis, placement, routing, logic ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $236K/yr
Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA) with BSEE, or * 8+ years of logic design experience (ASIC/FPGA) with MSEE Definite Plus: * ASIC ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $236K/yr
Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA) with BSEE, or * 8+ years of logic design experience (ASIC/FPGA) with MSEE Definite Plus: * ASIC ...
Experience with the ASIC design process and architecture of large SoCs or GPUs. * Programming and ... Digital Rights Management (DRM) standards * Security threat modelling and penetration testing
Experience with the ASIC design process and architecture of large SoCs or GPUs. * Programming and ... Digital Rights Management (DRM) standards * Security threat modelling and penetration testing
OR · Hybrid
Perform substrate breakout patterns for ASIC packages. * Optimize package pinout incorporating ... Constraint Manager) * Solid understanding of high-speed design signal integrity practices
FPGA/RTL Design Engineer - III (W2 Only)
$134K - $184K/yr
... managed services and direct placement services to Global 2000 Corporations. Collabera is ranked ... ASIC and/or SoC design flows and methodology, including CPF/UPF flows Experience with industry ...
FPGA/RTL Design Engineer - III (W2 Only)
$134K - $184K/yr
... managed services and direct placement services to Global 2000 Corporations. Collabera is ranked ... ASIC and/or SoC design flows and methodology, including CPF/UPF flows Experience with industry ...
Manage relationships between Lattice and customers by establishing relationships with key ... Minimum Qualifications * 7+ years' experience in FPGA and/or ASIC design, including experience ...
Manage relationships between Lattice and customers by establishing relationships with key ... Minimum Qualifications * 7+ years' experience in FPGA and/or ASIC design, including experience ...
Manage relationships between Lattice and customers by establishing relationships with key ... Minimum Qualifications * 7+ years' experience in FPGA and/or ASIC design, including experience ...
Manage relationships between Lattice and customers by establishing relationships with key ... Minimum Qualifications * 7+ years' experience in FPGA and/or ASIC design, including experience ...
Manage relationships between Lattice and customers by establishing relationships with key ... Minimum Qualifications * 7+ years' experience in FPGA and/or ASIC design, including experience ...
Manage relationships between Lattice and customers by establishing relationships with key ... Minimum Qualifications * 7+ years' experience in FPGA and/or ASIC design, including experience ...
Director, SoC Design Engineering
Hillsboro, OR · On-site
$148K - $180K/yr
... management experience - Expertise in SystemVerilog and UVM/OVM verification methodologies ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...
Director, SoC Design Engineering
Hillsboro, OR · On-site
$148K - $180K/yr
... management experience - Expertise in SystemVerilog and UVM/OVM verification methodologies ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...
Asic Design Manager information
See Oregon salary details
$44.4K - $59.7K
4% of jobs
$59.7K - $75.1K
8% of jobs
$86.3K is the 25th percentile. Wages below this are outliers.
$75.1K - $90.4K
17% of jobs
The median wage is $104.6K / yr.
$90.4K - $105.7K
22% of jobs
$105.7K - $121.1K
15% of jobs
$121.1K - $136.4K
6% of jobs
$141.3K is the 75th percentile. Wages above this are outliers.
$136.4K - $151.7K
7% of jobs
$151.7K - $167.1K
7% of jobs
$167.1K - $182.4K
8% of jobs
$182.4K - $197.7K
2% of jobs
$197.7K - $213K
2% of jobs
$44.4K
$121K
$213K
How much do asic design manager jobs pay per year?
As of Aug 6, 2026, the average yearly pay for asic design manager in Oregon is $121,050.00, according to ZipRecruiter salary data. Most workers in this role earn between $88,300.00 and $152,200.00 per year, depending on experience, location, and employer.
Is ASIC design in demand?
ASIC design is in high demand due to the growth of industries such as consumer electronics, telecommunications, and automotive technology. Skilled ASIC design managers with expertise in hardware description languages and verification tools are sought after to develop custom integrated circuits for various applications.
What is the difference between Asic Design Manager vs Asic Design Engineer?
| Aspect | Asic Design Manager | Asic Design Engineer |
|---|---|---|
| Responsibilities | Oversees ASIC design projects, manages teams, and coordinates with stakeholders | Performs ASIC design, coding, simulation, and verification tasks |
| Required Skills | Leadership, project management, ASIC design knowledge | Hardware description languages, circuit design, verification skills |
| Experience | Typically 8+ years in ASIC design, with leadership experience | Usually 2-5 years in ASIC design roles |
| Work Environment | Design teams, project planning, cross-functional collaboration | Design labs, simulation environments, coding and testing |
The main difference between an Asic Design Manager and an Asic Design Engineer lies in their roles. The manager oversees projects and teams, focusing on leadership and coordination, while the engineer concentrates on technical ASIC design and implementation. Both roles require ASIC design expertise, but the manager's role is more strategic and supervisory.
What are the key skills and qualifications needed to thrive as an ASIC Design Manager?
To thrive as an ASIC Design Manager, you need expertise in digital and analog ASIC design, project management experience, and typically a degree in electrical engineering or a related field. Familiarity with industry-standard EDA tools (such as Cadence or Synopsys), verification methodologies, and knowledge of relevant design flows is crucial. Strong leadership, communication, and problem-solving skills help manage teams and coordinate with cross-functional stakeholders. These competencies ensure high-quality chip designs are delivered on time and meet performance and cost targets, which is vital for organizational success.
Is ASIC design difficult?
ASIC design is a complex process that requires strong knowledge of digital logic, hardware description languages like VHDL or Verilog, and familiarity with electronic design automation tools. It involves multiple stages such as architecture, verification, and testing, making it challenging but manageable with proper training and experience.
What are some common challenges faced by an ASIC Design Manager in leading multidisciplinary teams?
ASIC Design Managers often navigate the complexities of coordinating multidisciplinary teams, including digital, analog, verification, and physical design engineers. One common challenge is ensuring clear communication across these specialties to maintain alignment on project goals, timelines, and technical requirements. Additionally, managing shifting priorities, resolving technical bottlenecks, and balancing resource allocation are frequent hurdles. Successful managers foster collaboration, set clear expectations, and leverage structured project management practices to keep teams productive and motivated.
What does an ASIC Design Manager do?
An ASIC Design Manager oversees the design and development of Application Specific Integrated Circuits (ASICs), managing a team of engineers through the entire chip design process. They coordinate project timelines, ensure technical specifications are met, and facilitate communication between design, verification, and manufacturing teams. Their role also involves resource planning, risk management, and ensuring that the final product meets performance, cost, and quality targets.
What are popular job titles related to Asic Design Manager jobs in Oregon? For Asic Design Manager jobs in Oregon, the most frequently searched job titles are:
What job categories do people searching Asic Design Manager jobs in Oregon look for? The top searched job categories for Asic Design Manager jobs in Oregon are:
What cities in Oregon are hiring for Asic Design Manager jobs? Cities in Oregon with the most Asic Design Manager job openings:
Full-time
Medical, Retirement, PTO
Re-posted 28 days ago
Intel rating
8.7
Based on 147 frontline employees who took The Breakroom Quiz
19th of 156 rated electronics manufacturers
Job description
Job Details:Job Description:
About Intel Foundry Services
Intel Foundry is a systems foundry dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. With a focus on scalability, AI advancement, and shaping the future, we provide an unparalleled blend of an industry-leading technology, a rich IP portfolio, a world-class design ecosystem, and an operationally resilient global manufacturing supply chain.
Position Overview
We seek a DFT Application Engineer to provide technical support to Intel Foundry Services customers on PDKs, DFT/DFM insertion, and ATPG validation methodologies. This critical role supports Aerospace, Defense, and Government (ADG) customers in achieving successful tape-outs while ensuring the highest quality standards through comprehensive DFT solutions and customer engagement.
Key Responsibilities
Customer Technical Support & Collaboration
- Provide comprehensive DFT tool/flow/methodology support to address customer issues and challenges, ensuring successful tape-outs and maximum customer satisfaction
- Work closely with internal Intel teams and external stakeholders including foundry customers' design teams, IP providers, and EDA vendors to resolve complex technical issues
- Deliver customer-facing technical support and guidance on DFT implementation strategies
DFT Methodology & Quality Leadership
- Drive quality improvements in ASIC DFT/DFM and ATPG validation methodology, capability/flow, and documentation for both block-level and SoC-level implementations
- Collaborate with RTL and Hard IP designers on DFT/DFM implementation methodology and work with physical designers on DFT/DFM physical implementation, validation, and timing signoff
- Develop and optimize DFT insertion flows for advanced CMOS processes and multi-die designs
Technical Content Development & Training
- Develop application notes, comprehensive documentation, and deliver technical training presentations to customers and internal teams
- Create best practice guidelines and methodology documentation for DFT implementation across various design complexities
- Support knowledge transfer and capability building for both internal teams and customer organizations
Essential Skills & Attributes
- Customer-Focused:Strong customer-oriented attitude and mindset with commitment to customer success
- Self-Motivated:Self-driven and results-oriented with ability to manage multiple complex tasks effectively
- Collaborative:Excellent teamwork skills to drive innovative solutions for customer design implementation challenges
- Analytical:Strong analytical problem-solving capabilities for complex DFT challenges
- Communication:Effective communication skills with experience in collaboration, active listening, and providing constructive technical feedback
The Minimum qualifications are required to be considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
- US Citizenship required
- Ability to obtain US Government Security Clearance
- Bachelor's degree in Electrical Engineering, Computer Engineering, or STEM-related field
- 3+ years of experience with advanced CMOS processes (22nm and below)
- 3+ years of combined experience in the following: implementing ASIC DFT/DFM insertion (MBIST, LBIST, SCAN, JTAG) at both ASIC design block level and full chip level, including ATPG validation and DFT timing/signoff at SOC level
- 2+ years of experience in one or more of the following scripting languages (Python, Perl, Tcl, and/or shell scripting)
Preferred Qualifications
- Active US Government Security Clearance with a minimum of Secret Level.
- Post-graduate degree in Electrical/Computer Engineering or STEM-related field
- Hands-on experience in Design Implementation and methodology (ASIC design, Fullchip Integration, Design Signoff, LVS, DRC, DFX/DFM, Reliability
- Proficiency with major EDA tools for MBIST insertion, hierarchical SCAN and JTAG insertion, DFT constraint generation and ATPG validation for single die and multi-die designs
- Experience building/developing quality DFT/DFX insertion flow and ATPG validation flow
- Experience providing technical direction to engineering teams and customer support
- Customer-facing experience in technical roles
- Experience with state-of-the-art process technology (7nm and below) and PDK-based technology evaluation
What We Offer
- Opportunity to work with cutting-edge DFT technologies for aerospace, defense, and government applications
- Direct customer engagement and technical leadership in advanced semiconductor design
- Access to Intel's most advanced foundry technologies and comprehensive EDA tool suites
- Competitive compensation
- Professional development in DFT methodologies and foundry services
- Direct impact on national security through advanced semiconductor technology solutions
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
About Intel
Sourced by ZipRecruiter
Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth
Industry
Manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1968