NVIDIA is seeking outstanding ASIC Verification Engineer to verify the world's leading GPUs. This ... design & implementation with focus on Memory Management unit, define the verification scope ...
NVIDIA is seeking outstanding ASIC Verification Engineer to verify the world's leading GPUs. This ... design & implementation with focus on Memory Management unit, define the verification scope ...
SoC Design and Verification
Hillsboro, OR · On-site
$148K - $180K/yr
Knowledge of ASIC design methodologies and flows. * Ability to Manage and conduct training for the team. * Worked with companies and seen at least a couple of tape-outs * Project management ...
SoC Design and Verification
Hillsboro, OR · On-site
$148K - $180K/yr
Knowledge of ASIC design methodologies and flows. * Ability to Manage and conduct training for the team. * Worked with companies and seen at least a couple of tape-outs * Project management ...
SoC Design and Verification
Hillsboro, OR · On-site
$148K - $180K/yr
Knowledge of ASIC design methodologies and flows * Ability to Manage and conduct training for the team * Worked with companies and seen at least a couple of tape-outs * Project management ...
SoC Design and Verification
Hillsboro, OR · On-site
$148K - $180K/yr
Knowledge of ASIC design methodologies and flows * Ability to Manage and conduct training for the team * Worked with companies and seen at least a couple of tape-outs * Project management ...
$190K - $280K/yr
This role also involves managing external physical design partners, driving tool and flow decisions ... years of experience in ASIC physical design for high-performance SoCs. * Proven end-to-end ...
Self-driven and results-oriented with ability to manage multiple complex tasks effectively ... Hands-on experience in Design Implementation and methodology (ASIC design, Fullchip Integration ...
Self-driven and results-oriented with ability to manage multiple complex tasks effectively ... Hands-on experience in Design Implementation and methodology (ASIC design, Fullchip Integration ...
As a senior analog design engineering manager, you will lead technical teams to deliver IP that ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...
As a senior analog design engineering manager, you will lead technical teams to deliver IP that ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...
Proven success managing long-cycle, highly technical, multi-stakeholder sales pursuits. * Strong ... Extensive network across the ASIC and broader semiconductor ecosystem, including IC design firms ...
Proven success managing long-cycle, highly technical, multi-stakeholder sales pursuits. * Strong ... Extensive network across the ASIC and broader semiconductor ecosystem, including IC design firms ...
Hardware Design Engineer
Hillsboro, OR · Hybrid
$106K - $198K/yr
Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently * Solid communication and project management skills * 5+ years of logic design experience * BSEE ...
Hardware Design Engineer
Hillsboro, OR · Hybrid
$106K - $198K/yr
Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently * Solid communication and project management skills * 5+ years of logic design experience * BSEE ...
Hardware Design Engineer
Hillsboro, OR · Hybrid
$106K - $198K/yr
Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently * Solid communication and project management skills * 5+ years of logic design experience * BSEE ...
Hardware Design Engineer
Hillsboro, OR · Hybrid
$106K - $198K/yr
Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently * Solid communication and project management skills * 5+ years of logic design experience * BSEE ...
Hardware Design Engineer
Hillsboro, OR · On-site
$106K - $198K/yr
Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently * Solid communication and project management skills * 5+ years of logic design experience * BSEE ...
Hardware Design Engineer
Hillsboro, OR · On-site
$106K - $198K/yr
Significant ASIC and/or FPGA design experience * Ability to learn quickly and work independently * Solid communication and project management skills * 5+ years of logic design experience * BSEE ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $236K/yr
Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA) with BSEE, or * 8+ years of logic design experience (ASIC/FPGA) with MSEE Definite Plus: * ASIC ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $236K/yr
Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA) with BSEE, or * 8+ years of logic design experience (ASIC/FPGA) with MSEE Definite Plus: * ASIC ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $236K/yr
Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA) with BSEE, or * 8+ years of logic design experience (ASIC/FPGA) with MSEE Definite Plus: * ASIC ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $236K/yr
Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA) with BSEE, or * 8+ years of logic design experience (ASIC/FPGA) with MSEE Definite Plus: * ASIC ...
FPGA Engineering Manager (Memory Test, Tualatin, OR)
Tualatin, OR · On-site
$171K - $273K/yr
... ASIC or FPGA design * Minimum of 5 years of experience as an FPGA/ASIC project lead, driving ... Experience as a first level manager of an engineering team. * Experience with FPGA Transceiver ...
FPGA Engineering Manager (Memory Test, Tualatin, OR)
Tualatin, OR · On-site
$171K - $273K/yr
... ASIC or FPGA design * Minimum of 5 years of experience as an FPGA/ASIC project lead, driving ... Experience as a first level manager of an engineering team. * Experience with FPGA Transceiver ...
Principal Logic Design Engineer
Hillsboro, OR · On-site
$127K - $236K/yr
Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA) with BSEE, or * 8+ years of logic design experience (ASIC/FPGA) with MSEE Definite Plus: * ASIC ...
Principal Logic Design Engineer
Hillsboro, OR · On-site
$127K - $236K/yr
Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA) with BSEE, or * 8+ years of logic design experience (ASIC/FPGA) with MSEE Definite Plus: * ASIC ...
Principal Logic Design Engineer
Hillsboro, OR · On-site
$127K - $236K/yr
Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA) with BSEE, or * 8+ years of logic design experience (ASIC/FPGA) with MSEE Definite Plus: * ASIC ...
Principal Logic Design Engineer
Hillsboro, OR · On-site
$127K - $236K/yr
Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA) with BSEE, or * 8+ years of logic design experience (ASIC/FPGA) with MSEE Definite Plus: * ASIC ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $236K/yr
Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA) with BSEE, or * 8+ years of logic design experience (ASIC/FPGA) with MSEE Definite Plus: * ASIC ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $236K/yr
Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA) with BSEE, or * 8+ years of logic design experience (ASIC/FPGA) with MSEE Definite Plus: * ASIC ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $236K/yr
Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA) with BSEE, or * 8+ years of logic design experience (ASIC/FPGA) with MSEE Definite Plus: * ASIC ...
Principal Logic Design Engineer
Hillsboro, OR · Hybrid
$127K - $236K/yr
Solid communication and project management skills * 10+ years of logic design experience (ASIC/FPGA) with BSEE, or * 8+ years of logic design experience (ASIC/FPGA) with MSEE Definite Plus: * ASIC ...
... generation and management. * Expertise in analysis and fixing of timing paths through ECOs ... Experience in physical design and optimization e.g., synthesis, placement, routing, logic ...
... generation and management. * Expertise in analysis and fixing of timing paths through ECOs ... Experience in physical design and optimization e.g., synthesis, placement, routing, logic ...
... managing technical execution for silicon projects. Solid foundational knowledge of analog design ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...
... managing technical execution for silicon projects. Solid foundational knowledge of analog design ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...
Experience with the ASIC design process and architecture of large SoCs or GPUs. * Programming and ... Digital Rights Management (DRM) standards * Security threat modelling and penetration testing
Experience with the ASIC design process and architecture of large SoCs or GPUs. * Programming and ... Digital Rights Management (DRM) standards * Security threat modelling and penetration testing
Asic Design Manager information
See Oregon salary details
$44.4K - $59.7K
4% of jobs
$59.7K - $75.1K
8% of jobs
$86.3K is the 25th percentile. Wages below this are outliers.
$75.1K - $90.4K
17% of jobs
The median wage is $104.6K / yr.
$90.4K - $105.7K
22% of jobs
$105.7K - $121.1K
15% of jobs
$121.1K - $136.4K
6% of jobs
$141.3K is the 75th percentile. Wages above this are outliers.
$136.4K - $151.7K
7% of jobs
$151.7K - $167.1K
7% of jobs
$167.1K - $182.4K
8% of jobs
$182.4K - $197.7K
2% of jobs
$197.7K - $213K
2% of jobs
$44.4K
$121K
$213K
How much do asic design manager jobs pay per year?
As of Jul 17, 2026, the average yearly pay for asic design manager in Oregon is $121,050.00, according to ZipRecruiter salary data. Most workers in this role earn between $88,300.00 and $152,200.00 per year, depending on experience, location, and employer.
What is the difference between Asic Design Manager vs Asic Design Engineer?
| Aspect | Asic Design Manager | Asic Design Engineer |
|---|---|---|
| Responsibilities | Oversees ASIC design projects, manages teams, and coordinates with stakeholders | Performs ASIC design, coding, simulation, and verification tasks |
| Required Skills | Leadership, project management, ASIC design knowledge | Hardware description languages, circuit design, verification skills |
| Experience | Typically 8+ years in ASIC design, with leadership experience | Usually 2-5 years in ASIC design roles |
| Work Environment | Design teams, project planning, cross-functional collaboration | Design labs, simulation environments, coding and testing |
The main difference between an Asic Design Manager and an Asic Design Engineer lies in their roles. The manager oversees projects and teams, focusing on leadership and coordination, while the engineer concentrates on technical ASIC design and implementation. Both roles require ASIC design expertise, but the manager's role is more strategic and supervisory.
What are the key skills and qualifications needed to thrive as an ASIC Design Manager, and why are they important?
To thrive as an ASIC Design Manager, you need expertise in digital and analog ASIC design, project management experience, and typically a degree in electrical engineering or a related field. Familiarity with industry-standard EDA tools (such as Cadence or Synopsys), verification methodologies, and knowledge of relevant design flows is crucial. Strong leadership, communication, and problem-solving skills help manage teams and coordinate with cross-functional stakeholders. These competencies ensure high-quality chip designs are delivered on time and meet performance and cost targets, which is vital for organizational success.
What are some common challenges faced by an ASIC Design Manager in leading multidisciplinary teams?
ASIC Design Managers often navigate the complexities of coordinating multidisciplinary teams, including digital, analog, verification, and physical design engineers. One common challenge is ensuring clear communication across these specialties to maintain alignment on project goals, timelines, and technical requirements. Additionally, managing shifting priorities, resolving technical bottlenecks, and balancing resource allocation are frequent hurdles. Successful managers foster collaboration, set clear expectations, and leverage structured project management practices to keep teams productive and motivated.
What does an ASIC Design Manager do?
An ASIC Design Manager oversees the design and development of Application Specific Integrated Circuits (ASICs), managing a team of engineers through the entire chip design process. They coordinate project timelines, ensure technical specifications are met, and facilitate communication between design, verification, and manufacturing teams. Their role also involves resource planning, risk management, and ensuring that the final product meets performance, cost, and quality targets.
What are popular job titles related to Asic Design Manager jobs in Oregon? For Asic Design Manager jobs in Oregon, the most frequently searched job titles are:
What job categories do people searching Asic Design Manager jobs in Oregon look for? The top searched job categories for Asic Design Manager jobs in Oregon are:
What cities in Oregon are hiring for Asic Design Manager jobs? Cities in Oregon with the most Asic Design Manager job openings:
Full-time
Posted yesterday
Nvidia rating
9.3
Based on 5 frontline employees who took The Breakroom Quiz
15th of 209 rated software companies
Job description
We are now looking for a Verification Engineer for our Memory Management Unit.
NVIDIA is seeking outstanding ASIC Verification Engineer to verify the world's leading GPUs. This position offers the opportunity to have a real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.
What you'll be doing:
As a member of our verification team, you'll understand the design & implementation with focus on Memory Management unit, define the verification scope, develop the verification infrastructure (Testbenches, BFMs, Checkers, Monitors), implement test/coverage plans, and verify the correctness of the design.
Collaborate with architects, designers, software engineers across sites to accomplish your goals.
Plan and work on strategic direction of the methodology for the testbench with advance methodology.
What we need to see:
You have Bachelors or Masters Degree in Electrical Engineering or Computer Science or Computer Engineering or equivalent experience
Exposure to Computer Architecture, ASIC design and verification methodology is required
Strong ability with SystemVerilog, C and/or C++, test planning, coverage closure, and creating reusable verification components.
Knowledgeable in constrained random testing with functional coverage and assertion-based verification.
Understanding of object oriented programming concepts.
Exposure to simulation tools like VCS, IES and debug tools like Debussy, GDB.
Strong interpersonal skills.
Good debugging and problem solving skills.
Ways to stand out from the crowd:
Understanding of memory subsystem micro-architecture, cache topologies and policies, memory management, interconnects, and/or arbiter designs is a huge plus.
Experience with Universal Verification Methodology (UVM), SystemVerilog checkers and scoreboards. Assertion-based verification, Semiformal Verification (SFV).
Perl or Python knowledge.
NVIDIA is widely considered to be one of the technology world's most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. Are you creative and autonomous? Do you love the challenge of crafting the highest performance & lowest power silicon possible? If so, we want to hear from you. Come join our GPU ASIC Verification team and help us build future architectures that will continue to drive us forward in the fields of High Performance Computing, Graphics and AI.
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 100,000 USD - 166,750 USD for Level 1, and 116,000 USD - 189,750 USD for Level 2.You will also be eligible for equity and benefits.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
About Nvidia
Sourced by ZipRecruiter
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology--and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1993