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Asic Design Manager Jobs in Oregon (NOW HIRING)

Intel

Mixed Signal Logic Design Engineer

Hillsboro, OR · On-site

Knowledge of Power Delivery and Power Management systems * Solid understanding of analog/mixed ... Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom ...

Intel

EDA Tools SW Engineer

Hillsboro, OR · Hybrid

$173K - $330K/yr

Technical management or lead experience mentoring or leading medium sized teams. * Experience with ... Industry direct experience and in-depth knowledge to support customers in ASIC/Physical Design and ...

New

Rambus

SPE Hardware Architecture

Hillsboro, OR · On-site

$189K - $352K/yr

Work closely with logic design, verification and physical design teams to define implementation ... Knowledge of front-end ASIC development flow and best practices * Knowledge of system architecture ...

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All JobsAsic Design JobsAsic Design Manager JobsAsic Design Manager Jobs in Oregon

Asic Design Manager information

See Oregon salary details

$44.4K

$121K

$213K

How much do asic design manager jobs pay per year?

As of Aug 6, 2026, the average yearly pay for asic design manager in Oregon is $121,050.00, according to ZipRecruiter salary data. Most workers in this role earn between $88,300.00 and $152,200.00 per year, depending on experience, location, and employer.

Is ASIC design in demand?

ASIC design is in high demand due to the growth of industries such as consumer electronics, telecommunications, and automotive technology. Skilled ASIC design managers with expertise in hardware description languages and verification tools are sought after to develop custom integrated circuits for various applications.

What is the difference between Asic Design Manager vs Asic Design Engineer?

AspectAsic Design ManagerAsic Design Engineer
ResponsibilitiesOversees ASIC design projects, manages teams, and coordinates with stakeholdersPerforms ASIC design, coding, simulation, and verification tasks
Required SkillsLeadership, project management, ASIC design knowledgeHardware description languages, circuit design, verification skills
ExperienceTypically 8+ years in ASIC design, with leadership experienceUsually 2-5 years in ASIC design roles
Work EnvironmentDesign teams, project planning, cross-functional collaborationDesign labs, simulation environments, coding and testing

The main difference between an Asic Design Manager and an Asic Design Engineer lies in their roles. The manager oversees projects and teams, focusing on leadership and coordination, while the engineer concentrates on technical ASIC design and implementation. Both roles require ASIC design expertise, but the manager's role is more strategic and supervisory.

What are the key skills and qualifications needed to thrive as an ASIC Design Manager?

To thrive as an ASIC Design Manager, you need expertise in digital and analog ASIC design, project management experience, and typically a degree in electrical engineering or a related field. Familiarity with industry-standard EDA tools (such as Cadence or Synopsys), verification methodologies, and knowledge of relevant design flows is crucial. Strong leadership, communication, and problem-solving skills help manage teams and coordinate with cross-functional stakeholders. These competencies ensure high-quality chip designs are delivered on time and meet performance and cost targets, which is vital for organizational success.

Is ASIC design difficult?

ASIC design is a complex process that requires strong knowledge of digital logic, hardware description languages like VHDL or Verilog, and familiarity with electronic design automation tools. It involves multiple stages such as architecture, verification, and testing, making it challenging but manageable with proper training and experience.

What are some common challenges faced by an ASIC Design Manager in leading multidisciplinary teams?

ASIC Design Managers often navigate the complexities of coordinating multidisciplinary teams, including digital, analog, verification, and physical design engineers. One common challenge is ensuring clear communication across these specialties to maintain alignment on project goals, timelines, and technical requirements. Additionally, managing shifting priorities, resolving technical bottlenecks, and balancing resource allocation are frequent hurdles. Successful managers foster collaboration, set clear expectations, and leverage structured project management practices to keep teams productive and motivated.

What does an ASIC Design Manager do?

An ASIC Design Manager oversees the design and development of Application Specific Integrated Circuits (ASICs), managing a team of engineers through the entire chip design process. They coordinate project timelines, ensure technical specifications are met, and facilitate communication between design, verification, and manufacturing teams. Their role also involves resource planning, risk management, and ensuring that the final product meets performance, cost, and quality targets.
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Asic Design Manager jobs near you
Infographic showing various Asic Design Manager job openings in Oregon as of August 2026, with employment types broken down into 74% Full Time, 25% Part Time, and 1% Contract. Highlights an 84% Physical, 3% Hybrid, and 13% Remote job distribution, with an average salary of $121,050 per year, or $58.2 per hour.

FPGA Engineering Manager (MTD, Tualatin, OR)

Teradyne

Tualatin, OR

$155K - $248K/yr

Other

Medical, Dental, Vision, Life, Retirement, PTO

Posted 25 days ago

Job description

We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world!

We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive.

Our Purpose
TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought within our workforce. Our employees are supported to innovate and learn something new every day.
We cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team - one that makes better decisions, drives innovation and delivers better business results.

Opportunity Overview

 

Teradyne's Memory Test Division (MTD) seeks a motivated and technically driven FPGA Manager to support the development of our growing portfolio of cutting-edge memory test solutions.

MTD creates advanced solutions for complex testing applications, driving innovation through creativity and diverse perspectives. Our test instrumentation supports the world's most advanced memory technologies, combining state-of-the-art digital and analog designs, cutting-edge ASIC/FPGA technologies, liquid cooling, and high-performance signal delivery.

We are looking for a hands-on FPGA Engineering Manager to oversee the development of cutting-edge memory test solutions. This role combines technical oversight, project management and direct engineering contributions, ensuring the successful delivery of high-quality, reliable products that support the world's most advanced memory technologies.

Your key responsibilities as FPGA Engineering Manager will be:

  • Plan, prioritize, and manage multiple FPGA development projects, ensuring on-time delivery within budget and scope.
  • Represent the FPGA team on project core teams and at program reviews.
  • Provide support for sustaining issues.
  • Work closely with cross-functional teams, including hardware, software, and firmware engineers, to ensure seamless integration of FPGA designs into larger systems.
  • Recruit, onboard, and retain top engineering talent to build a high-performing team.
  • Set goals and conduct regular performance conversations for a team of 4 to 6 engineers.
  • Contribute to FPGA team process improvement initiatives.
  • Provide hands-on technical guidance to the FPGA engineering team, including reviewing and contributing to FPGA architectures, designs, and specifications.
  • Actively participate in FPGA design and development, including RTL coding, synthesis, timing closure, and lab validation.

All About You
We seek individuals who share our passion. Our commitment to customer success drives us to go the extra mile. If you're ready to join us in this mission, take a closer look at the minimum criteria for the position.

  • B.S. or M.S. in Electrical Engineering or closely related discipline
  • 12+ years of relevant experience in Digital ASIC or FPGA design
  • Minimum of 5 years of experience as an FPGA/ASIC project lead, driving multiple projects through concept development, architectural exploration, design implementation, lab validation, and production release. 
  • Extensive experience coding RTL (verilog preferred). 
  • Extensive experience using digital simulation tools (Cadence preferred). 
  • Extensive experience using static timing analysis tools. 
  • Experience designing with the following: PCIe, DDR3/4/5, AXI, ethernet, SPI, SERDES 
  • Experience with either AMD or Altera FPGAs and development tools (Vivado/Quartus), preferably both. 
  • Experience using digital design quality tools e.g. Lint, CDC. 
  • Experience with bug tracking tools
  • Experience with source control systems and continuous integration. 
  • Familiarity with digital verification tools and methodologies (preferably UVM). 
  • Experience with project scheduling tools
  • Excellent presentation and communication skills. 

Additional Desired Skills:

  • Experience developing hardware for automated test equipment 
  • Experience as a first level manager of an engineering team.   
  • Experience with FPGA Transceiver based designs
  • Experience with DRAM and Flash Memory interfaces
  • Experience with Linux and Windows operating systems
  • Familiarity with ATE instrumentation

Compensation: The base salary range for this role is$155,500-$248,700.This range is a good faith estimate, and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location. 

Incentive Plan: This job is eligible for discretionary bonus(es) based on financial performance.

Benefits: Teradyne offers a variety of robust health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more. Please click here to see details.

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