Analog IC Design Engineer
Cupertino, CA · On-site
Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... as it applies to analog IC designsProven working experience in using spectrum analyzers ...
Cupertino, CA · On-site
Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... as it applies to analog IC designsProven working experience in using spectrum analyzers ...
Cupertino, CA · On-site
Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... as it applies to analog IC designsProven working experience in using spectrum analyzers ...
Santa Clara, CA · On-site
$156K - $160K/yr
Responsible for full-custom analog IC layout and physical verification (DRC/ANT/DFM/ERC/LVS) using industry-standard tools like Cadence Virtuoso and Calibre. * Execute top-level layout and coordinate ...
Santa Clara, CA · On-site
$156K - $160K/yr
Responsible for full-custom analog IC layout and physical verification (DRC/ANT/DFM/ERC/LVS) using industry-standard tools like Cadence Virtuoso and Calibre. * Execute top-level layout and coordinate ...
Santa Clara, CA · On-site
$156K - $160K/yr
Responsible for full-custom analog IC layout and physical verification (DRC/ANT/DFM/ERC/LVS) using industry-standard tools like Cadence Virtuoso and Calibre. * Execute top-level layout and coordinate ...
Santa Clara, CA · On-site
$156K - $160K/yr
Responsible for full-custom analog IC layout and physical verification (DRC/ANT/DFM/ERC/LVS) using industry-standard tools like Cadence Virtuoso and Calibre. * Execute top-level layout and coordinate ...
Responsible for full-custom analog IC layout and physical verification (DRC/ANT/DFM/ERC/LVS) using industry-standard tools like Cadence Virtuoso and Calibre. * Execute top-level layout and coordinate ...
Quick apply
Responsible for full-custom analog IC layout and physical verification (DRC/ANT/DFM/ERC/LVS) using industry-standard tools like Cadence Virtuoso and Calibre. * Execute top-level layout and coordinate ...
Cupertino, CA · On-site
Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... as it applies to analog IC designsProven working experience in using spectrum analyzers ...
Cupertino, CA · On-site
Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... as it applies to analog IC designsProven working experience in using spectrum analyzers ...
Colorado Springs, CO · On-site
$117K - $195K/yr
... Analog IC Layout experience * 5+ years of experience with Cadence Virtuoso Layout XL tools including cell level design and top-level verification tasks including full-chip DRC, LVS and metal density ...
Colorado Springs, CO · On-site
$117K - $195K/yr
... Analog IC Layout experience * 5+ years of experience with Cadence Virtuoso Layout XL tools including cell level design and top-level verification tasks including full-chip DRC, LVS and metal density ...
$117K - $195K/yr
... Analog IC Layout experience * 5+ years of experience with Cadence Virtuoso Layout XL tools including cell level design and top-level verification tasks including full-chip DRC, LVS and metal density ...
$117K - $195K/yr
... Analog IC Layout experience * 5+ years of experience with Cadence Virtuoso Layout XL tools including cell level design and top-level verification tasks including full-chip DRC, LVS and metal density ...
$117K - $195K/yr
... Analog IC Layout experience * 5+ years of experience with Cadence Virtuoso Layout XL tools including cell level design and top-level verification tasks including full-chip DRC, LVS and metal density ...
$117K - $195K/yr
... Analog IC Layout experience * 5+ years of experience with Cadence Virtuoso Layout XL tools including cell level design and top-level verification tasks including full-chip DRC, LVS and metal density ...
Cupertino, CA · On-site
Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... as it applies to analog IC designsProven working experience in using spectrum analyzers ...
Cupertino, CA · On-site
Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... as it applies to analog IC designsProven working experience in using spectrum analyzers ...
Santa Clara, CA · On-site
$237K/yr
Role: Analog Layout Engineer Location: Santa Clara, CA (Remote Option available) Duration ... Responsibilities include leading IC layout of cutting-edge high-performance, high-speed CMOS ...
Santa Clara, CA · On-site
$237K/yr
Role: Analog Layout Engineer Location: Santa Clara, CA (Remote Option available) Duration ... Responsibilities include leading IC layout of cutting-edge high-performance, high-speed CMOS ...
The team has an exciting opportunity for a IC Layout Design Engineer V to join our diverse team ... Efficiently laying out sensitive RF, Analog and Mixed Signal circuits conforming to all physical ...
The team has an exciting opportunity for a IC Layout Design Engineer V to join our diverse team ... Efficiently laying out sensitive RF, Analog and Mixed Signal circuits conforming to all physical ...
The Integrated Circuit Engineer designs and develops microwave, analog, digital, and mixed-signal ... IC layout execution and supervision of IC layout design specialists. * Works with characterization ...
Quick apply
The Integrated Circuit Engineer designs and develops microwave, analog, digital, and mixed-signal ... IC layout execution and supervision of IC layout design specialists. * Works with characterization ...
$181K - $318K/yr
Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... it applies to analog IC designs Proven working experience in using spectrum analyzers ...
$181K - $318K/yr
Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... it applies to analog IC designs Proven working experience in using spectrum analyzers ...
$181K - $318K/yr
Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... it applies to analog IC designs Proven working experience in using spectrum analyzers ...
$181K - $318K/yr
Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... it applies to analog IC designs Proven working experience in using spectrum analyzers ...
Cupertino, CA · On-site
$126K - $220K/yr
Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... it applies to analog IC designs Proven working experience in using spectrum analyzers ...
Cupertino, CA · On-site
$126K - $220K/yr
Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... it applies to analog IC designs Proven working experience in using spectrum analyzers ...
San Jose, CA · On-site
$114K - $213K/yr
The lead Analog IC Designer is responsible for the design and development of analog/mixed signal IC ... Position requires proficiency in using CAD tools for circuit simulation, layout, and physical ...
San Jose, CA · On-site
$114K - $213K/yr
The lead Analog IC Designer is responsible for the design and development of analog/mixed signal IC ... Position requires proficiency in using CAD tools for circuit simulation, layout, and physical ...
$181K - $318K/yr
Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... it applies to analog IC designs Proven working experience in using spectrum analyzers ...
$181K - $318K/yr
Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... it applies to analog IC designs Proven working experience in using spectrum analyzers ...
$126K - $220K/yr
Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... it applies to analog IC designs Proven working experience in using spectrum analyzers ...
$126K - $220K/yr
Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... it applies to analog IC designs Proven working experience in using spectrum analyzers ...
$171K - $302K/yr
Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... it applies to analog IC designs Proven working experience in using spectrum analyzers ...
$171K - $302K/yr
Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... it applies to analog IC designs Proven working experience in using spectrum analyzers ...
$181K - $318K/yr
Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... it applies to analog IC designs Proven working experience in using spectrum analyzers ...
$181K - $318K/yr
Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... it applies to analog IC designs Proven working experience in using spectrum analyzers ...
$100.5K - $111.8K
14% of jobs
$117.2K is the 25th percentile. Wages below this are outliers.
$111.8K - $123.1K
24% of jobs
The median wage is $130.3K / yr.
$123.1K - $134.5K
20% of jobs
$141.9K is the 75th percentile. Wages above this are outliers.
$134.5K - $145.8K
27% of jobs
$145.8K - $157.1K
0% of jobs
$157.1K - $168.4K
0% of jobs
$168.4K - $179.7K
0% of jobs
$179.7K - $191K
4% of jobs
$191K - $202.4K
4% of jobs
$202.4K - $213.7K
3% of jobs
$213.7K - $225K
4% of jobs
$100.5K
$142.4K
$225K
| Aspect | Analog IC Layout | Digital IC Layout |
|---|---|---|
| Design Focus | Continuous signal processing, precision | Binary signal processing, logic |
| Complexity | High, due to analog component interactions | Moderate to high, depending on logic complexity |
| Tools & Techniques | Specialized analog layout tools, parasitic extraction | Standard digital EDA tools, place & route |
| Work Environment | Cleanroom, high precision | Cleanroom, logic optimization |
Analog IC Layout involves designing circuits that handle continuous signals with high precision, requiring specialized tools and techniques. Digital IC Layout focuses on binary logic circuits, often with more standardized processes. Both roles demand a strong understanding of semiconductor fabrication and layout design, but they differ in complexity and focus areas.

8.1
Based on 661 frontline employees who took The Breakroom Quiz
6th of 30 rated technology retailers
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Computer and electronic product manufacturing
10,000+ Employees
Cupertino, CA, US
1976