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Ai Chip Design Rtl Jobs in Illinois (NOW HIRING)

Cadence Design Systems Inc.

Lead Design Engineer

Cary, IL

$104K - $136K/yr

... Chip (SOC). This role is to implement, verify, timing closure to tape out Palladium and Protium ... Work on RTL synthesis and floorplanning * Build clock trees and perform optimizations * Close ...

Eliyan

PD - Principal, Physical Design

Mundelein, IL · On-site

You will drive the development of cutting-edge ASICs from RTL to GDSII. You will work with a cross ... Drive clock constraint quality across hierarchy with clean chip to block and block to chip handoff ...

Eliyan

DFT - Staff DFT Engineer

Mundelein, IL · On-site

... design flexibility. You will be defining and implementing scan, memory BIST, IEEE 1149.x/1687/1500 ... chip_level and stand-alone IP blocks such as PHYs and chiplets) * Implement DFT features in RTL for ...

Eliyan

Architecture - I/O Architect

Mundelein, IL · On-site

... design flexibility. You will drive the definition and development of cutting-edge ASICs from RTL to ... Expertise in multiple areas of architecture definition, chip micro-architecture, protocol ...

Edgehog Trading

Junior FPGA Developer

Chicago, IL · On-site

Design, implement, and verify RTL logic in Verilog or SystemVerilog targeting ultra-low-latency ... Use AI tools to accelerate your development workflow - RTL review, testbench generation, debugging ...

DRW

Senior FPGA Engineer (Algo)

Chicago, IL · On-site

$150K - $250K/yr

Strong skills in RTL logic design (Verilog) and verification; 2+ years of experience writing ... Experience with the design of system-on-chip (SOC) architectures, memory & processor subsystems ...

Syntiant

Product Compliance Intern

Itasca, IL · On-site

$38K - $47K/yr

Syntiant Corp., a leader in the high-growth AI software and semiconductor solutions space, is ... Syntiant's advanced chip solutions merge deep learning with semiconductor design to produce ultra ...

Syntiant

Product Compliance Intern

Itasca, IL · On-site

$38K - $47K/yr

Syntiant Corp., a leader in the high-growth AI software and semiconductor solutions space, is ... Syntiant's advanced chip solutions merge deep learning with semiconductor design to produce ultra ...

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All JobsAi Chip Design Rtl JobsAi Chip Design Rtl Jobs in Illinois

Ai Chip Design Rtl information

What is a $900000 AI job?

A $900,000 AI job typically refers to a high-level position in artificial intelligence, such as senior AI researcher, machine learning engineer, or AI architect, often requiring advanced skills in deep learning, neural networks, and hardware design like RTL for AI chips. Such roles usually involve leadership, extensive experience, and may include stock options or bonuses, with compensation reflecting expertise and impact on AI hardware development.

What is the difference between Ai Chip Design Rtl vs Ai Chip Verification Engineer?

AspectAi Chip Design RtlAi Chip Verification Engineer
Primary FocusDeveloping and implementing Register Transfer Level (RTL) code for AI chipsVerifying and validating RTL designs to ensure functionality
Skills RequiredHDL languages (Verilog/VHDL), digital design, FPGA/ASIC knowledgeSimulation, testbench creation, debugging, scripting skills
Work EnvironmentDesign teams, hardware development labs, EDA toolsVerification teams, simulation environments, test setups
CertificationsHardware design certifications, FPGA/ASIC trainingVerification methodologies, UVM, SystemVerilog certifications

While Ai Chip Design Rtl focuses on creating the hardware description code for AI chips, Ai Chip Verification Engineer ensures that the RTL design functions correctly through rigorous testing. Both roles require knowledge of HDL languages and work closely within hardware development teams, but their core responsibilities differ—design versus verification.

Will AI replace RTL designers?

AI chip design RTL (Register Transfer Level) development involves creating hardware descriptions that require expert knowledge of digital logic and hardware architecture. While AI tools can assist in automating certain tasks like code generation and verification, they are unlikely to fully replace RTL designers, as human expertise is essential for complex decision-making, optimization, and ensuring design correctness. RTL designers will continue to play a critical role in the chip design process, often working alongside AI-assisted tools to improve efficiency and innovation.

What are some common challenges faced by AI Chip Design RTL engineers during the verification process?

AI Chip Design RTL engineers often encounter challenges in ensuring their designs meet complex functional and performance requirements, especially given the rapid pace of AI hardware advancements. Verification can be particularly demanding due to the need to simulate and test intricate AI workloads, manage large datasets, and debug subtle timing or logic errors. Collaboration with verification teams, system architects, and software engineers is essential to address these issues efficiently and to ensure seamless integration of the RTL code into the broader chip design. Staying up-to-date with the latest verification tools and methodologies is also crucial for success in this role.

Which 3 jobs will survive AI?

AI Chip Design RTL professionals are likely to continue in demand due to the specialized technical skills required for hardware description languages like Verilog and VHDL, which are less easily automated. Jobs involving complex problem-solving, system integration, and hardware-software interface design, such as hardware engineers, system architects, and verification engineers, are also expected to persist. These roles require domain expertise and critical thinking that complement AI automation capabilities.

What are AI Chip Design RTL engineers?

AI Chip Design RTL (Register Transfer Level) engineers are specialists who design the digital logic for chips used in artificial intelligence applications. They use hardware description languages like Verilog or VHDL to create and validate the architecture and functionality of these chips before they are manufactured. Their work ensures that AI processors are efficient, high-performing, and meet the requirements of modern AI workloads. RTL engineers collaborate closely with verification, software, and hardware teams to optimize chip performance and power consumption.

What is the salary of RTL design?

The salary for an RTL (Register Transfer Level) design engineer typically ranges from $80,000 to $150,000 annually, depending on experience, location, and company size. Entry-level positions may start lower, while experienced engineers with specialized skills in hardware description languages like VHDL or Verilog can earn higher salaries.

What are the key skills and qualifications needed to thrive as an AI Chip Design RTL Engineer, and why are they important?

To thrive as an AI Chip Design RTL Engineer, you need a solid background in digital design, computer architecture, and proficiency in Hardware Description Languages (HDLs) like Verilog or VHDL, often supported by a degree in electrical or computer engineering. Experience with simulation tools (e.g., ModelSim, Synopsys), ASIC/FPGA design flows, and relevant certifications are highly valued. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help you excel in collaborative and complex design environments. These competencies are crucial for creating efficient, reliable AI hardware that meets performance and power requirements in a fast-evolving field.
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Ai Chip Design Rtl jobs near you
Principal AI Forward Deployment Engineer

Principal AI Forward Deployment Engineer

Cadence Design Systems Inc.

Cary, IL

Full-time

Posted 2 days ago

Cadence Design Systems rating

9.0

Company rating: 9.0 out of 10

Based on 5 frontline employees who took The Breakroom Quiz

33rd of 245 rated software companies

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Role Summary

Cadence is hiring a Principal AI Forward Deployment Engineer to embed with strategic semiconductor customers and operationalize Cadence's AI and agentic solutions across their end-to-end silicon design flows. This is a senior, customer-facing applied-AI role for an experienced chip-design practitioner who can translate front-end, physical-design, and methodology workflows into concrete, measurable productivity wins powered by flagship LLMs and Cadence AI tooling. You will be the trusted technical lead at the customer who turns 'AI for chip design' from a slideware promise into a deployed, adopted, and ROI-positive reality.

Why This Role Exists

  • Customers are racing to apply LLMs and agentic AI to RTL, verification, implementation, and signoff - but they need a partner who deeply understands *both* their tape-out flows and how to wield modern AI systems.
  • This role owns the last mile: taking Cadence AI products (AgentStack, BU Super-Agents, Cadence.AI / JEDAI platform, Cerebrus, Verisium, Allegro X AI, etc.) and making them work inside the customer's actual methodology, PDKs, compute fabric, and security boundaries.
  • Success here directly accelerates customer tape-outs, expands Cadence AI footprint, and feeds product roadmaps with real-world signal.

What You Will Do

  • Customer-Embedded Deployment. Lead end-to-end deployment of Cadence AI / LLM-powered solutions into the customer's silicon design flows - from RTL design and verification through synthesis, place-and-route, timing, power, signoff, and packaging.
  • Applied AI for Chip Design. Architect and tune agentic workflows, prompt strategies, RAG pipelines, and tool-calling patterns on top of flagship LLMs (Claude, GPT, Gemini, Llama, Qwen, etc.) to automate real EDA tasks - debug triage, constraint authoring, ECO loops, PD recipe tuning, methodology Q&A, log/report summarization, and design-review copilots.
  • Methodology & Flow Integration. Map customer methodology (FE design, DV, PD, CAD, signoff) onto Cadence AI building blocks; identify the highest-ROI insertion points; build reference flows the customer's CAD/methodology team can own long-term.
  • Productivity & ROI Ownership. Define and report KPIs - cycle-time reduction, engineer-hours saved, iteration count, first-pass success, license/compute efficiency. Own the story from pilot to production rollout across BUs and sites.
  • Trusted Technical Advisor. Be the senior technical face to customer fellows, methodology leads, and design-team principals. Run design reviews, technical readouts, and joint roadmaps. Translate customer pain into actionable feedback for Cadence R&D and AI platform teams.
  • AI Systems Enablement (plus). Where needed, guide customer IT/InfoSec on secure LLM access patterns, on-prem vs. gateway deployment, model routing, prompt/response logging, data-egress controls, and GPU/inference capacity planning.
  • Knowledge Multiplier. Capture playbooks, reference designs, and 'golden prompts' so every deployment compounds. Mentor field AEs, FAEs, and customer champions.

Must-Have Qualifications

  • BS/MS/PhD in EE, ECE, CS, or related discipline.
  • 10+ years of hands-on semiconductor / chip design experience in one or more of: front-end design (RTL, micro-architecture, DV), physical design / implementation (synthesis, P&R, timing, power, signoff), CAD / methodology / flow development, or design execution / project technical leadership on production tape-outs.
  • Deep, practitioner-level fluency with industry EDA flows and pain points - you have personally shipped silicon and know where the cycle-time and engineer-time really go.
  • Demonstrated ability to apply LLMs / AI tools to get real engineering work done (e.g., agent-based debug, code/RTL generation assist, scripted automation, copilots, RAG over design docs/logs). Doesn't have to be your title - has to be your reflex.
  • Excellent customer-facing communication: equally credible with a staff RTL engineer, a PD methodology lead, and a CAD / design-enablement leader.
  • Bias to action, ownership, and shipping. Comfortable being the single throat-to-choke for a customer-facing AI deployment.
  • Based in or willing to relocate to Portland, OR; able to be on-site at customer locations as the engagement requires.

Nice-to-Have / Bonus

  • Prior experience as a Cadence / Synopsys / Siemens EDA customer power user, AE, or methodology architect.
  • Hands-on with at least one agentic framework (Claude Code, Cursor, LangGraph, AutoGen, custom MCP/tool-calling stacks) applied to engineering workflows.
  • Experience standing up secure enterprise LLM access (gateways, model routing, key management, audit logging) for engineering orgs.
  • Familiarity with GPU/inference infrastructure, vLLM/TGI/Triton, fine-tuning / LoRA / SLM workflows, and evaluation harnesses for code/EDA tasks.
  • Background in low-power, high-performance, AI/ML, networking, automotive, or HPC silicon programs.
  • Public artifacts - papers, talks, OSS, or internal champions - showing applied AI in EDA/silicon contexts.
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