... design engineers and digital engineers to create/optimize layouts of complex blocks and chip-level ... Knowledge of scripting with Linux shell, Makefile, Modules, SKILL, TCL, Python and/or AI-LLM ...
... design engineers and digital engineers to create/optimize layouts of complex blocks and chip-level ... Knowledge of scripting with Linux shell, Makefile, Modules, SKILL, TCL, Python and/or AI-LLM ...
... design engineers and digital engineers to create/optimize layouts of complex blocks and chip-level ... Knowledge of scripting with Linux shell, Makefile, Modules, SKILL, TCL, Python and/or AI-LLM ...
... design engineers and digital engineers to create/optimize layouts of complex blocks and chip-level ... Knowledge of scripting with Linux shell, Makefile, Modules, SKILL, TCL, Python and/or AI-LLM ...
Software Engineer
Orlando, FL · On-site
$79K - $118K/yr
Contributing to software engineering initiatives with software design & development, software test ... Experience using AI-assisted tools for programming, code review, and productivity enhancement
Software Engineer
Orlando, FL · On-site
$79K - $118K/yr
Contributing to software engineering initiatives with software design & development, software test ... Experience using AI-assisted tools for programming, code review, and productivity enhancement
Software Engineer
Orlando, FL · On-site
$79K - $118K/yr
Contributing to software engineering initiatives with software design & development, software test ... Experience using AI-assisted tools for programming, code review, and productivity enhancement
Software Engineer
Orlando, FL · On-site
$79K - $118K/yr
Contributing to software engineering initiatives with software design & development, software test ... Experience using AI-assisted tools for programming, code review, and productivity enhancement
Ai Chip Design Rtl information
What is the difference between Ai Chip Design Rtl vs Ai Chip Verification Engineer?
| Aspect | Ai Chip Design Rtl | Ai Chip Verification Engineer |
|---|---|---|
| Primary Focus | Developing and implementing Register Transfer Level (RTL) code for AI chips | Verifying and validating RTL designs to ensure functionality |
| Skills Required | HDL languages (Verilog/VHDL), digital design, FPGA/ASIC knowledge | Simulation, testbench creation, debugging, scripting skills |
| Work Environment | Design teams, hardware development labs, EDA tools | Verification teams, simulation environments, test setups |
| Certifications | Hardware design certifications, FPGA/ASIC training | Verification methodologies, UVM, SystemVerilog certifications |
While Ai Chip Design Rtl focuses on creating the hardware description code for AI chips, Ai Chip Verification Engineer ensures that the RTL design functions correctly through rigorous testing. Both roles require knowledge of HDL languages and work closely within hardware development teams, but their core responsibilities differ—design versus verification.
What are common challenges faced by AI Chip Design RTL engineers during the verification process?
What is an AI Chip Design RTL engineer?
What skills and qualifications are needed to thrive as an AI Chip Design RTL engineer?
Qorvo rating
8.3
Based on 21 frontline employees who took The Breakroom Quiz
Job description
Qorvo (Nasdaq: QRVO) supplies innovative semiconductor solutions that make a better world possible. We combine product and technology leadership, systems-level expertise and global manufacturing scale to quickly solve our customers' most complex technical challenges. Qorvo serves multiple high-growth segments of large global markets, including consumer electronics, smart home/IoT, automotive, EVs, battery-powered appliances, network infrastructure, healthcare and aerospace/defense. Visit www.qorvo.com to learn how our innovative team is helping connect, protect and power our planet.
Summary
As Staff Layout Designer, you will work as part of a cross-functional, global team delivering System-on-Chip (SoC) products from concept to high volume production for the consumer, industrial, and automotive industries.
Responsibilities
Work with analog/RF/mixed-signal design engineers and digital engineers to create/optimize layouts of complex blocks and chip-level SoC macros
Work on continuous-improvement projects to automate/customize layout work flows through scripting and batch-mode operations
Produce high quality analog/RF/mixed-signal macros using industry best practices for layout and physical verification
Own block-level layout designs and top-level floor planning including full hierarchical verification/debug
Lead, document, and communicate layout design flows and reviews efficiently including the tape-out process and project database management/archive
Help manage/support layout contractors and mentor junior layout designers
Collaborate with global team engineers/designers to ensure designs are specification compliant and on time
Work independently on complex tasks while staying in sync with team activities/plan
Qualifications
Minimum of Associate's degree in Electronic Engineering or related field (Bachelor's degree preferred)
5+ years relevant industry work experience required
Strong working skills with Cadence Virtuoso and PDK layout design tools (OA, CDL, GDS).
Strong working skills with physical verification tools (Pegasus/Calibre) and flows (DRC, LVS, ERC, PERC, LVL)
Detailed experience with analog/RF/mixed-signal layout in deep sub-micron, CMOS nodes (40nm and lower)
Understanding of LDE, ANT, ESD/LUP, NTN/TW/SOI isolation, matching, PnR parasitics, and EMIR concepts
Knowledge of digital physical design flows and techniques (VHDL, Verilog, LEF, DEF)
Knowledge of scripting with Linux shell, Makefile, Modules, SKILL, TCL, Python and/or AI-LLM clients
This position is not eligible for visa sponsorship by the Company.
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MAKE A DIFFERENCE AT QORVO
We are Qorvo. We do more than create innovative RF and Power solutions for the mobile, defense and infrastructure markets - we are a place to innovate and shape the future of wireless communications. It starts with our employees. As a unified global team, we bring a commitment to excellence, growth and a passion for creating what's next. Explore the possibilities with us.
We are an Equal Employment Opportunity (EEO) employer and welcome all qualified applicants. Applicants will receive fair and impartial consideration without regard to any characteristics protected by applicable law, including race, color, religion, sex (as defined by law), national origin, age, military or veteran status, genetic information, or disability.
About Qorvo
Sourced by ZipRecruiter
Industry
Manufacturing and manufacturing
Company size
5,001 - 10,000 Employees
Headquarters location
Greensboro, NC, US
Year founded
1957