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Astera Labs

60 Astera Labs System Validation Engineer Jobs Hiring Near You

Astera Labs

Performance Engineer

San Jose, CA · On-site

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity ... systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom ...

Astera Labs

Product Quality Engineer (NCG)

San Jose, CA · On-site

$120K - $140K/yr

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity ... Collaborate with design, validation, hardware, and system engineering teams to resolve quality ...

Astera Labs

Principal Product Engineer

San Jose, CA · On-site

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity ... Strong problem-solving skills that involve system level analysis with test hardware, test program ...

Astera Labs

Distinguished Formal Verification

San Jose, CA · On-site

$159K/yr

... systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom ... Astera Labs is seeking a Distinguished Engineer, Formal Verification to join our world-class ...

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Infographic showing various System Validation Engineer job openings at Astera Labs in the United States as of September 2026, with employment types broken down into 99% Full Time, and 1% Part Time. Highlights an 97% Physical, 1% Hybrid, and 2% Remote job distribution.

Sr. Principal Program Manager, ASIC Post-Silicon Engineering

San Jose, CA • On-site

Astera Labs
Semiconductor and Electronic Component Manufacturing • 11 - 50 employees
Learn more about Astera Labsexternal

$136K - $136K/yr

Full-time

Re-posted 15 days ago

Job description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Role Overview
Astera Labs is seeking a Sr. Principal Program Manager, ASIC Post-Silicon Engineering to lead execution of complex post-silicon programs for AI connectivity products. This role owns cross-functional program delivery from silicon power-on through bring-up, validation, qualification, customer sampling, and release to manufacturing - RTM, aligning engineering execution with product, customer, and business milestones.
The ideal candidate brings deep experience leading technically complex semiconductor or systems programs involving silicon, firmware, software, platform, validation, manufacturing, and customer readiness. They are highly effective at driving cross-functional alignment, managing program risk, and communicating crisply with both engineering teams and executive stakeholders.
Key Responsibilities
  • Program Ownership and Execution
    • Own the integrated post-silicon program plan from silicon power-on through bring-up, validation, qualification, customer sampling, and RTM, ensuring alignment across silicon, firmware/software, platform, compliance, production test and manufacturing milestones.
    • Drive program schedules, budgets, resources, interdependencies, and risk management, balancing scope, schedule, and cost trade-offs while maintaining clear communication with executives and key stakeholders.
    • Drive validation readiness and execution alignment for high-speed connectivity products, including validation plan coverage, firmware and hardware readiness, test content, platform availability, and milestone tracking for technologies such as PCIe, Ethernet, SerDes, and platform-level interconnect solutions.
    • Manage phase-gate exit criteria, readiness checkpoints, dashboards, and decision forums to support predictable delivery and rapid cross-functional decision-making.
  • Stakeholder Management and Cross-Functional Leadership
    • Lead cross-functional execution across engineering, product, operations, quality, manufacturing, and customer-facing teams.
    • Drive internal technical issue resolution through structured triage, escalation management, milestone reviews, and executive reporting; surface risks early, drive accountability, and enable timely decisions and recovery plans.
    • Align priorities, trade-offs, readiness criteria, and launch decisions with business and customer goals across stakeholders.
  • Customer Sampling and Release to Manufacturing
    • Own customer sampling readiness, including sample allocation, validation exit criteria, firmware/software readiness, known-issue documentation, errata, release notes, reference platforms, and validation summaries.
    • Drive customer-facing issue resolution and escalation management in partnership with product management, applications engineering, sales, quality, and engineering teams, ensuring materials and support plans are aligned with deployment.
    • Lead cross-functional execution from engineering validation through RTM phase-gate exit.
    • Partner with product engineering, test engineering, operations, manufacturing, supply chain, and quality teams to drive manufacturing readiness reviews, production ramp execution, and production-release approvals, including ATE readiness, characterization, yield learning, failure analysis, reliability qualification, waivers, and errata.

Basic Qualifications
  • 10+ years of experience in semiconductor engineering, post-silicon validation, system validation, silicon bring-up, product engineering, product applications, FAE, or technical program management with a strong technical background.
  • Strong experience leading post-silicon execution for complex ASIC, SoC, FPGA, SerDes, Ethernet, PCIe, CXL, networking, AI infrastructure, cloud, data center, or high-performance compute products.
  • Demonstrated ability to manage products from first silicon through validation, customer sampling, qualification, RTM, and manufacturing readiness.
  • Deep understanding of silicon validation flows, including bring-up, debug, characterization, interoperability, compliance, regression execution and issue triage.
  • Experience managing FW development cycle, experience with JIRA, Confluence, dashboards, issue-tracking systems.
  • Experience working with cross-functional teams across architecture, silicon design, firmware, software, electrical validation, system validation, product engineering, test, manufacturing, quality, operations, applications engineering, and customer-facing organizations.
  • Strong technical knowledge in one or more of the following:
    • High-speed SerDes
    • Ethernet, PCIe, CXL, NVMe, or similar protocols
    • AI server, networking, or data center platforms
    • Signal integrity, eye diagrams, jitter, noise, impedance, and link training
    • FEC, protocol compliance, and interoperability validation
    • Firmware/hardware/software interaction
    • Board, platform, and system-level debug
    • Electrical validation and lab-based debug
    • Optical or Active electrical modules
  • Proven experience managing executive communications, program dashboards, milestones, dependencies, technical risks, issue escalations, and launch-readiness reviews.
  • Ability to operate effectively in fast-paced, ambiguous, technically complex environments with aggressive product schedules.

Salary range is $205,000 to $250,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

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