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Astera Labs

60 Astera Labs Digital Design Engineer Jobs Hiring Near You

Astera Labs

Senior Product Engineer

San Jose, CA · On-site

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity ... You'll work across the full product lifecycle, partnering with design, applications, and operations ...

Astera Labs

Technical Lead Power Engineer

San Jose, CA · On-site

$160K - $200K/yr

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity ... design engineering, with a focus on ASIC or high-speed digital designs. * Technical Skills:

Astera Labs

Principal Product Engineer

San Jose, CA · On-site

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity ... Digital and analog circuit level understanding for DUT * Excellent team player with great ...

Astera Labs

Product Quality Engineer (NCG)

San Jose, CA · On-site

$120K - $140K/yr

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity ... Collaborate with design, validation, hardware, and system engineering teams to resolve quality ...

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Infographic showing various Digital Design Engineer job openings at Astera Labs in the United States as of August 2026, with employment types broken down into 100% Full Time. Highlights an 95% Physical, 2% Hybrid, and 3% Remote job distribution.

Principal Engineering Program Manager (EPM)

Astera Labs

San Jose, CA • On-site

$160K - $200K/yr

Full-time

This job post has expired today. Applications are no longer accepted.

Job description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Principal Engineering Program Manager, (EPM)
Location: San Jose, CA (Onsite)
Role Overview
As a Principal Engineering Program Manager on our Analog/Mixed-Signal (AMS) team, you will drive the execution of the complex silicon programs that power Astera Labs' purpose-built connectivity solutions. You'll orchestrate multi-disciplinary teams - spanning circuit design, layout, verification, and silicon validation - to deliver high-performance AMS IP on schedule, on budget, and to spec.
This is a high-impact leadership role at a hyper-growth company defining the connectivity backbone of the AI era. You'll own program plans from concept through tape-out and silicon bring-up, surface and resolve cross-functional risks, and bring the operational rigor that turns ambitious engineering into products shipping at rack scale. Your ability to align stakeholders and keep fast-moving programs on track will be central to Astera's continued momentum.
Key Responsibilities
  • Program Planning & Execution
    • Define, drive, and maintain end-to-end program schedules for AMS IP development, from specification through tape-out and validation
    • Manage critical path, milestones, and dependencies across circuit design, layout, verification, and silicon bring-up
    • Establish and track program metrics, budgets, and deliverables to ensure predictable, high-quality outcomes
  • Cross-Functional Leadership
    • Partner with AMS design, digital, systems, product, and operations teams to align priorities and resolve blockers
    • Lead program reviews, drive decision-making, and communicate status, risks, and trade-offs to leadership and stakeholders
    • Coordinate with external partners, foundries, and vendors on tape-out readiness and schedule commitments
  • Risk Management & Process Excellence
    • Proactively identify, quantify, and mitigate technical and schedule risks across concurrent programs
    • Drive continuous improvement of program management processes, tools, and best practices for AMS execution
    • Champion clear documentation, accountability, and operational discipline across the program lifecycle
Basic Qualifications
  • Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field
  • 8+ years of experience in program or project management within semiconductor, IC, or hardware development
  • Proven track record managing complex silicon or AMS/IP programs through tape-out and silicon validation
  • Strong understanding of the ASIC/IC development lifecycle, including design, verification, layout, and bring-up
  • Excellent stakeholder management, communication, and cross-functional leadership skills
  • Proficiency with program management and collaboration tools (e.g., Microsoft Project, Microsoft 365)
Preferred Qualifications
  • MS in Electrical Engineering, Computer Engineering, or a related field
  • Direct experience with analog/mixed-signal or high-speed connectivity programs
  • PMP certification or equivalent program management credential
  • Familiarity with foundry engagement, tape-out flows, and vendor/IP coordination
  • Ability to thrive and lead through ambiguity in a fast-paced, hyper-growth environment

Salary range is $160,000 to $200,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

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