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60 Astera Labs Digital Design Engineer Jobs Hiring Near You

Astera Labs

Product Tech Lead

San Jose, CA

$160K - $200K/yr

Astera Labs is hiring a Tech Lead Design Engineer to help architect and deliver the connectivity ... digital design experience, including at least one full chip from spec to tapeout * Strong ...

Astera Labs

Performance Engineer

San Jose, CA · On-site

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity ... Design, build, and maintain automated lab infrastructure including test execution pipelines ...

Astera Labs

Distinguished Formal Verification

San Jose, CA · On-site

$159K/yr

Serve as technical authority on formal verification, providing expert guidance to engineering leadership on risk mitigation and design quality * Represent Astera Labs in industry forums, standards ...

Astera Labs

Technical Lead Power Engineer

San Jose, CA · On-site

$160K - $200K/yr

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity ... design engineering, with a focus on ASIC or high-speed digital designs. * Technical Skills:

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Infographic showing various Digital Design Engineer job openings at Astera Labs in the United States as of September 2026, with employment types broken down into 99% Full Time, and 1% Part Time. Highlights an 97% Physical, 1% Hybrid, and 2% Remote job distribution.

Product Tech Lead

San Jose, CA

Astera Labs
Semiconductor and Electronic Component Manufacturing • 11 - 50 employees
Learn more about Astera Labsexternal

$160K - $200K/yr

Full-time

Re-posted 6 days ago

Job description

Astera Labs is hiring a Tech Lead Design Engineer to help architect and deliver the connectivity silicon powering the world's largest AI clusters. You'll own design execution on complex blocks across our purpose-built products, working at the cutting edge of PCIe, CXL, Ethernet, and emerging rack-scale interconnect technologies.

This is a high-impact technical role at a hyper-growth company. You'll partner closely with architecture, verification, DFT, and physical design teams to take features from spec to silicon, while contributing to the design methodology that scales with our roadmap. If you want to ship silicon that defines AI infrastructure, this is the team.

Key Responsibilities
  • RTL Design & Implementation
    • Own RTL design for assigned blocks from microarchitecture through synthesis sign-off
    • Develop high-quality, synthesizable Verilog/SystemVerilog with strong attention to PPA
    • Drive design reviews, lint, CDC, and timing closure activities to silicon-ready quality
  • Cross-Functional Execution
    • Partner with architecture to translate specifications into implementation-ready microarchitecture
    • Collaborate with verification on testplans, coverage closure, and bug triage
    • Work with DFT and physical design teams on scan, BIST, floorplanning, and timing closure
  • Technical Leadership & Quality
    • Mentor junior engineers and contribute to design methodology, scripts, and best practices
    • Debug complex pre-silicon and post-silicon issues across RTL, gate-level, and emulation environments
    • Drive structured, data-driven design decisions in support of aggressive tapeout schedules
Basic Qualifications
  • Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
  • 5+ years of digital design experience, including at least one full chip from spec to tapeout
  • Strong proficiency in Verilog/SystemVerilog, RTL coding, and synthesis flows
  • Hands-on experience with timing closure, CDC, lint, and low-power design techniques
  • Solid understanding of high-speed serial interfaces (PCIe, Ethernet, or similar) and SoC integration
Preferred Qualifications
  • MS or PhD in Electrical Engineering or Computer Engineering
  • Experience with PCIe Gen5/Gen6, CXL, UALink, UCIe, or Ethernet MAC/PCS designs
  • Familiarity with formal verification, emulation, or assertion-based methodologies
  • Background in advanced process nodes (7nm, 5nm, or below)
  • Strong debug skills across pre-silicon and post-silicon environments

The base salary range is $160,000 USD - $200,000 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

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