ACL Digital
ACL Digital

60 Acl Digital Product Engineer Jobs Hiring Near You

System IP / RTL Design Engineer

Austin, TX

$99K - $135K/yr

Experienced in Silicon bring-up activities Experienced in timing and coverage closure Proficient with UNIX/Linux and programming languages such as PERL, Python, TCL, and Unix Shell Scripting Prior ...

At an entry level, performs drafting and/or engineering support duties. This position develops ... office productivity applications (such as email, word processing, spreadsheets, etc.) Skill in ...

Design Verification Engineer

Bodega Bay, CA · On-site

$161K - $197K/yr

Responsibilities: * Develop and maintain UVM-based verification environments * Verify CPU subsystems and instruction execution * Implement constrained-random testing * Integrate Instruction Set ...

* 10+ years of experience in High-Speed Analog Mixed-Signal layouts * Full-custom layout, verification & RC extraction experience. Top-level floorplan, powerplan & integration experience is a must

In Production Engineering, we need highly responsible professionals committed to upholding the highest standards of safety, quality, and integrity. Primary responsibilities: Investigates and develops ...

Create drafted parts and product structures to support operational and quality concerns. * Performs model definition changes within the defined engineering based on engineering input. Translating the ...

Improve developer productivity tools. Board Support Packages * Develop and maintain BSP components. * Enable new hardware platforms. * Support hardware bring-up and validation. * Work with hardware ...

Create drafted parts and product structures to support operational and quality concerns. * Performs model definition changes within the defined engineering based on engineering input. Translating the ...

Showing results 41-60

System IP / RTL Design Engineer

ACL Digital

Austin, TX

$99K - $135K/yr

Full-time

Re-posted 4 days ago


Job description

Job Description
Vertical
Technical
Description
Key responsibilities include: Work on RTL design of System IP blocks Work independently while closely collaborating with other designers as well as members of verification, physical design, performance and power teams Work on developing and maintaining Front-End Tools, Flows and Methodologies Work on creating scripts that automate repetitive daily tasks of team members Support Silicon bring-up activities
Requirements
Minimum requirements: Proficient in RTL design using Verilog and System Verilog Experienced in setting up and maintaining front-end tools for Synthesis, LEC, Lint and Low Power Analysis Excellent debug and problem-solving skills. Experienced in Silicon bring-up activities Experienced in timing and coverage closure Proficient with UNIX/Linux and programming languages such as PERL, Python, TCL, and Unix Shell Scripting Prior experience of having worked with interconnects, caches and/or cache coherency would be an added advantage Preferred candidate will possess the following: Verilog/System Verilog GIT Perl Python Tcl/Tk C/C++ Jenkins, Jira


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About ACL Digital

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ACL Digital is a global digital technology firm based in San Jose, CA, US, operating within the IT and services industry. The company offers a broad spectrum of services and solutions, including digital transformation, product engineering, industry solutions, and design-led experiences, among others. ACL Digital has its roots established in 1991 with the aim to become a leading-edge innovator in the digital space and has since grown significantly to work with an array of global customers. The company's mission incorporates a commitment to aiding customers to achieve their business goals by adopting and accelerating their digital transformation journeys.

Industry

Technology, communication and media

Company size

1,001 - 5,000 Employees

Headquarters location

San Jose, CA, US

Year founded

1992