Since we are developing a power-sensitive client product, you will drive performance/power ... Experience designing with multiple power domains and UPF. Preferred Qualifications * Experience ...

60 Sva Product Designer Jobs Hiring Near You
Since we are developing a power-sensitive client product, you will drive performance/power ... Experience designing with multiple power domains and UPF. Preferred Qualifications * Experience ...
SoC Design Engineer
$156K - $160K/yr
Be responsible for digital design of ASIC cores within image sensor SoC products, including IP ... Conduct design verification and modeling using SVA, Python, Perl, C++/C, and HLS. Work with digital ...
SoC Design Engineer
$156K - $160K/yr
Be responsible for digital design of ASIC cores within image sensor SoC products, including IP ... Conduct design verification and modeling using SVA, Python, Perl, C++/C, and HLS. Work with digital ...
Lead SoC Design Engineer
Los Altos, CA · On-site
$190 - $230/hr
Since we are developing a power-sensitive client product, you will drive performance/power ... Experience designing with multiple power domains and UPF. Preferred Qualifications * Experience ...
Lead SoC Design Engineer
Los Altos, CA · On-site
$190 - $230/hr
Since we are developing a power-sensitive client product, you will drive performance/power ... Experience designing with multiple power domains and UPF. Preferred Qualifications * Experience ...
... digital designs using advanced formal methods. This position offers the opportunity to work on ... Develop and maintain formal verification environments using SystemVerilog Assertions (SVA) and ...
... digital designs using advanced formal methods. This position offers the opportunity to work on ... Develop and maintain formal verification environments using SystemVerilog Assertions (SVA) and ...
Design Verification Engineer - Internal IP
Austin, TX · On-site
$120 - $160/hr
With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video ... You will collaborate with architects, RTL designers, and SW/FW/emulation teams to validate ...
Design Verification Engineer - Internal IP
Austin, TX · On-site
$120 - $160/hr
With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video ... You will collaborate with architects, RTL designers, and SW/FW/emulation teams to validate ...
Formal Verification Engineer
San Jose, CA · On-site
$350K/yr
Role Overview We are seeking a highly capable Formal Verification Engineer to join our core product ... Use formal verification tools to analyze RTL designs, prove design correctness, and identify ...
Formal Verification Engineer
San Jose, CA · On-site
$350K/yr
Role Overview We are seeking a highly capable Formal Verification Engineer to join our core product ... Use formal verification tools to analyze RTL designs, prove design correctness, and identify ...
... designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to ... Proficient in Verilog, System Verilog, SVA, C/C++, UVM, OOP, and working in Linux and Windows ...
New
... designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to ... Proficient in Verilog, System Verilog, SVA, C/C++, UVM, OOP, and working in Linux and Windows ...
New
Engineer, Staff|6155
San Diego, CA · On-site
... designs (PCIe, USB, MIPI, CXL, C2C, D2D, DDR, PLL, DAC, ADC, Sensors, etc.) for exciting products ... Author assertions in SVA, develop testcases, coverage models, debug and ensure coverage closure.
Engineer, Staff|6155
San Diego, CA · On-site
... designs (PCIe, USB, MIPI, CXL, C2C, D2D, DDR, PLL, DAC, ADC, Sensors, etc.) for exciting products ... Author assertions in SVA, develop testcases, coverage models, debug and ensure coverage closure.
CPU CDC/RDC/STA Engineer
Santa Clara, CA · On-site
$180 - $240/hr
... product! Description In this role, you will be: * Responsible for developing, improving, and maintaining the CDC and RDC sign-offs for CPU designs * Working with RTL and DV teams to recommend System ...
CPU CDC/RDC/STA Engineer
Santa Clara, CA · On-site
$180 - $240/hr
... product! Description In this role, you will be: * Responsible for developing, improving, and maintaining the CDC and RDC sign-offs for CPU designs * Working with RTL and DV teams to recommend System ...
... digital designs using advanced formal methods. This position offers the opportunity to work on ... Develop and maintain formal verification environments using SystemVerilog Assertions (SVA) and ...
... digital designs using advanced formal methods. This position offers the opportunity to work on ... Develop and maintain formal verification environments using SystemVerilog Assertions (SVA) and ...
SoC Design Engineer
Santa Clara, CA · On-site
$156K - $160K/yr
Be responsible for digital design of ASIC cores within image sensor SoC products, including IP ... Conduct design verification and modeling using SVA, Python, Perl, C++/C, and HLS. Work with digital ...
SoC Design Engineer
Santa Clara, CA · On-site
$156K - $160K/yr
Be responsible for digital design of ASIC cores within image sensor SoC products, including IP ... Conduct design verification and modeling using SVA, Python, Perl, C++/C, and HLS. Work with digital ...
Lead SoC Design Engineer
Los Altos, CA · On-site
Since we are developing a power-sensitive client product, you will drive performance/power ... Experience designing with multiple power domains and UPF. Preferred Qualifications * Experience ...
Lead SoC Design Engineer
Los Altos, CA · On-site
Since we are developing a power-sensitive client product, you will drive performance/power ... Experience designing with multiple power domains and UPF. Preferred Qualifications * Experience ...
... digital designs using advanced formal methods. This position offers the opportunity to work on ... Develop and maintain formal verification environments using SystemVerilog Assertions (SVA) and ...
... digital designs using advanced formal methods. This position offers the opportunity to work on ... Develop and maintain formal verification environments using SystemVerilog Assertions (SVA) and ...
Design Verification Engineer - Internal IP
San Jose, CA · On-site
$2.0K/mo
Our first products are heavily focused on inference . Backed by hundreds of millions from top-tier ... You will collaborate with architects, RTL designers, and SW/FW/emulation teams to validate ...
Design Verification Engineer - Internal IP
San Jose, CA · On-site
$2.0K/mo
Our first products are heavily focused on inference . Backed by hundreds of millions from top-tier ... You will collaborate with architects, RTL designers, and SW/FW/emulation teams to validate ...
SoC Design Engineer
Santa Clara, CA · On-site
$156K - $160K/yr
Be responsible for digital design of ASIC cores within image sensor SoC products, including IP ... Conduct design verification and modeling using SVA, Python, Perl, C++/C, and HLS. Work with digital ...
SoC Design Engineer
Santa Clara, CA · On-site
$156K - $160K/yr
Be responsible for digital design of ASIC cores within image sensor SoC products, including IP ... Conduct design verification and modeling using SVA, Python, Perl, C++/C, and HLS. Work with digital ...
... digital designs using advanced formal methods. This position offers the opportunity to work on ... Develop and maintain formal verification environments using SystemVerilog Assertions (SVA) and ...
... digital designs using advanced formal methods. This position offers the opportunity to work on ... Develop and maintain formal verification environments using SystemVerilog Assertions (SVA) and ...
Senior Formal Verification Engineer
Mountain View, CA · Hybrid
$123K - $169K/yr
Own the formal verification sign-off approach across complex IP and SoC designs, utilizing advanced ... Develop and deploy reusable formal testbenches, methodology flows, and high-coverage SVA assertion ...
Senior Formal Verification Engineer
Mountain View, CA · Hybrid
$123K - $169K/yr
Own the formal verification sign-off approach across complex IP and SoC designs, utilizing advanced ... Develop and deploy reusable formal testbenches, methodology flows, and high-coverage SVA assertion ...
Formal Verification Engineer
San Jose, CA · On-site
$150 - $350/hr
Role Overview We are seeking a highly capable Formal Verification Engineer to join our core product ... Use formal verification tools to analyze RTL designs, prove design correctness, and identify ...
Formal Verification Engineer
San Jose, CA · On-site
$150 - $350/hr
Role Overview We are seeking a highly capable Formal Verification Engineer to join our core product ... Use formal verification tools to analyze RTL designs, prove design correctness, and identify ...
At Apple, new ideas have a way of becoming extraordinary products, services, and customer ... designs. • Work closely with architecture and RTL designers on verifying the functionality ...
At Apple, new ideas have a way of becoming extraordinary products, services, and customer ... designs. • Work closely with architecture and RTL designers on verifying the functionality ...
Design Verification Engineer - Internal IP
San Jose, CA · On-site
$120 - $160/hr
Our first products are heavily focused on inference . Backed by hundreds of millions from top-tier ... You will collaborate with architects, RTL designers, and SW/FW/emulation teams to validate ...
Design Verification Engineer - Internal IP
San Jose, CA · On-site
$120 - $160/hr
Our first products are heavily focused on inference . Backed by hundreds of millions from top-tier ... You will collaborate with architects, RTL designers, and SW/FW/emulation teams to validate ...
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Job description
Summary
We're a well-funded, stealth startup building a next-generation, end-to-end computing platform powered by a custom, high-performance edge SoC on an advanced process node. By integrating flagship compute IP into an industry-leading design, we are building the optimized silicon foundation for our software platform from the ground up.
We're building a tight-knit, experienced in-house team to drive engineering outcomes and partner with a Tier-1 ASIC design house through the process. As our Lead SoC Design Engineer, you will develop the microarchitecture, own the critical tradeoffs required to hit aggressive PPA targets, and spearhead the implementation of key subsystems.
Responsibilities
- Microarchitecture: Author detailed microarchitecture documents and drive reviews with software, architecture and verification teams.
- Drive PPA targets: Since we are developing a power-sensitive client product, you will drive performance/power tradeoffs using a data-driven approach to hit aggressive targets.
- Partner with verification team: Participate in reviews of verification and emulation test plans to ensure successful first-pass silicon.
- RTL design: Own RTL coding, Lint/CDC/RDC checks, SDC and VCLP checks, and ensure that the design can be taken through physical design to meet frequency and power requirements.
Minimum Requirements
- 10+ years of experience in developing complex ASICs in advanced nodes.
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent experience.
- Deep knowledge of industry-standard on-chip interconnect protocols (AMBA AXI/AXI-S/APB).
- Experienced with Verilog, SystemVerilog, SystemVerilog Assertions (SVA).
- Proficiency in writing and debugging SDC timing constraints, including multi-cycle paths, false paths, and clock domain crossing constraints.
- Experience with industry-standard ASIC CAD tools for simulation, synthesis, STA, Lint, LEC, CDC, RDC, and power estimation.
- Experience designing with multiple power domains and UPF.
Preferred Qualifications
- Experience with commercial IP integration, ranging from high-speed interfaces (UCIe, DDR) to processing subsystems (CPU, GPU).
- Experience working directly with Arm cores and subsystems.
About Anodize
Sourced by ZipRecruiter
Industry
Motor vehicle manufacturing
Company size
11 - 50 Employees
Headquarters location
Ocala, FL, US