... digital designs using advanced formal methods. This position offers the opportunity to work on ... Develop and maintain formal verification environments using SystemVerilog Assertions (SVA) and ...

60 Sva Product Designer Jobs Hiring Near You
... digital designs using advanced formal methods. This position offers the opportunity to work on ... Develop and maintain formal verification environments using SystemVerilog Assertions (SVA) and ...
Formal Verification Engineer
San Jose, CA · On-site
$350K/yr
Role Overview We are seeking a highly capable Formal Verification Engineer to join our core product ... Use formal verification tools to analyze RTL designs, prove design correctness, and identify ...
Formal Verification Engineer
San Jose, CA · On-site
$350K/yr
Role Overview We are seeking a highly capable Formal Verification Engineer to join our core product ... Use formal verification tools to analyze RTL designs, prove design correctness, and identify ...
Lead SoC Design Engineer
Los Altos, CA · On-site
Since we are developing a power-sensitive client product, you will drive performance/power ... Experience designing with multiple power domains and UPF. Preferred Qualifications * Experience ...
Lead SoC Design Engineer
Los Altos, CA · On-site
Since we are developing a power-sensitive client product, you will drive performance/power ... Experience designing with multiple power domains and UPF. Preferred Qualifications * Experience ...
Engineer, Staff|6155
San Diego, CA · On-site
... designs (PCIe, USB, MIPI, CXL, C2C, D2D, DDR, PLL, DAC, ADC, Sensors, etc.) for exciting products ... Author assertions in SVA, develop testcases, coverage models, debug and ensure coverage closure.
Engineer, Staff|6155
San Diego, CA · On-site
... designs (PCIe, USB, MIPI, CXL, C2C, D2D, DDR, PLL, DAC, ADC, Sensors, etc.) for exciting products ... Author assertions in SVA, develop testcases, coverage models, debug and ensure coverage closure.
SoC Design Engineer
Santa Clara, CA · On-site
$156K - $160K/yr
Be responsible for digital design of ASIC cores within image sensor SoC products, including IP ... Conduct design verification and modeling using SVA, Python, Perl, C++/C, and HLS. Work with digital ...
SoC Design Engineer
Santa Clara, CA · On-site
$156K - $160K/yr
Be responsible for digital design of ASIC cores within image sensor SoC products, including IP ... Conduct design verification and modeling using SVA, Python, Perl, C++/C, and HLS. Work with digital ...
... digital designs using advanced formal methods. This position offers the opportunity to work on ... Develop and maintain formal verification environments using SystemVerilog Assertions (SVA) and ...
... digital designs using advanced formal methods. This position offers the opportunity to work on ... Develop and maintain formal verification environments using SystemVerilog Assertions (SVA) and ...
... digital designs using advanced formal methods. This position offers the opportunity to work on ... Develop and maintain formal verification environments using SystemVerilog Assertions (SVA) and ...
... digital designs using advanced formal methods. This position offers the opportunity to work on ... Develop and maintain formal verification environments using SystemVerilog Assertions (SVA) and ...
Design Verification Engineer - Internal IP
San Jose, CA · On-site
$2.0K/mo
Our first products are heavily focused on inference . Backed by hundreds of millions from top-tier ... You will collaborate with architects, RTL designers, and SW/FW/emulation teams to validate ...
Design Verification Engineer - Internal IP
San Jose, CA · On-site
$2.0K/mo
Our first products are heavily focused on inference . Backed by hundreds of millions from top-tier ... You will collaborate with architects, RTL designers, and SW/FW/emulation teams to validate ...
Senior Formal Verification Engineer
Mountain View, CA · Hybrid
$123K - $169K/yr
Own the formal verification sign-off approach across complex IP and SoC designs, utilizing advanced ... Develop and deploy reusable formal testbenches, methodology flows, and high-coverage SVA assertion ...
Senior Formal Verification Engineer
Mountain View, CA · Hybrid
$123K - $169K/yr
Own the formal verification sign-off approach across complex IP and SoC designs, utilizing advanced ... Develop and deploy reusable formal testbenches, methodology flows, and high-coverage SVA assertion ...
Design Verification Engineer - Internal IP
San Jose, CA · On-site
$150K - $275K/yr
Our first products are heavily focused on inference . Backed by hundreds of millions from top-tier ... You will collaborate with architects, RTL designers, and SW/FW/emulation teams to validate ...
Design Verification Engineer - Internal IP
San Jose, CA · On-site
$150K - $275K/yr
Our first products are heavily focused on inference . Backed by hundreds of millions from top-tier ... You will collaborate with architects, RTL designers, and SW/FW/emulation teams to validate ...
CPU Debug and Power Management Verification Engineer
Beaverton, OR · On-site
$141K/yr
At Apple, new ideas have a way of becoming extraordinary products, services, and customer ... designs. • Work closely with architecture and RTL designers on verifying the functionality ...
CPU Debug and Power Management Verification Engineer
Beaverton, OR · On-site
$141K/yr
At Apple, new ideas have a way of becoming extraordinary products, services, and customer ... designs. • Work closely with architecture and RTL designers on verifying the functionality ...
Design Verification Engineer - Internal IP
San Jose, CA · On-site
$2.0K/mo
Our first products are heavily focused on inference . Backed by hundreds of millions from top-tier ... You will collaborate with architects, RTL designers, and SW/FW/emulation teams to validate ...
Quick apply
Design Verification Engineer - Internal IP
San Jose, CA · On-site
$2.0K/mo
Our first products are heavily focused on inference . Backed by hundreds of millions from top-tier ... You will collaborate with architects, RTL designers, and SW/FW/emulation teams to validate ...
At Apple, new ideas have a way of becoming extraordinary products, services, and customer ... designs. • Work closely with architecture and RTL designers on verifying the functionality ...
At Apple, new ideas have a way of becoming extraordinary products, services, and customer ... designs. • Work closely with architecture and RTL designers on verifying the functionality ...
CPU CDC/STA Engineer
$150K - $277K/yr
At Apple, new ideas have a way of becoming extraordinary products, services, and customer ... CPU designs • Working with RTL and DV teams to recommend System Verilog assertions needed to ...
CPU CDC/STA Engineer
$150K - $277K/yr
At Apple, new ideas have a way of becoming extraordinary products, services, and customer ... CPU designs • Working with RTL and DV teams to recommend System Verilog assertions needed to ...
CPU CDC/STA Engineer
$129K - $194K/yr
At Apple, new ideas have a way of becoming extraordinary products, services, and customer ... CPU designs • Working with RTL and DV teams to recommend System Verilog assertions needed to ...
CPU CDC/STA Engineer
$129K - $194K/yr
At Apple, new ideas have a way of becoming extraordinary products, services, and customer ... CPU designs • Working with RTL and DV teams to recommend System Verilog assertions needed to ...
CPU Debug and Power Management Verification Engineer
Beaverton, OR · On-site
$141K/yr
At Apple, new ideas have a way of becoming extraordinary products, services, and customer ... designs. • Work closely with architecture and RTL designers on verifying the functionality ...
CPU Debug and Power Management Verification Engineer
Beaverton, OR · On-site
$141K/yr
At Apple, new ideas have a way of becoming extraordinary products, services, and customer ... designs. • Work closely with architecture and RTL designers on verifying the functionality ...
Hardware Emulation Engineer
Sunnyvale, CA · On-site
... designs to life. As an HVA Emulation Engineer, you will be at the forefront of pre-silicon ... into production. Responsibilities * Emulation Environment Development: Build and maintain pre ...
Hardware Emulation Engineer
Sunnyvale, CA · On-site
... designs to life. As an HVA Emulation Engineer, you will be at the forefront of pre-silicon ... into production. Responsibilities * Emulation Environment Development: Build and maintain pre ...
Lead Formal Verification Engineer
Austin, TX · On-site
$156K/yr
It can heal us, entertain us, and make us more connected, productive, and understanding of the ... designs. * Proven expertise in SystemVerilog Assertions (SVA), property development, and abstract ...
Lead Formal Verification Engineer
Austin, TX · On-site
$156K/yr
It can heal us, entertain us, and make us more connected, productive, and understanding of the ... designs. * Proven expertise in SystemVerilog Assertions (SVA), property development, and abstract ...
At Apple, new ideas have a way of becoming extraordinary products, services, and customer ... designs. • Work closely with architecture and RTL designers on verifying the functionality ...
At Apple, new ideas have a way of becoming extraordinary products, services, and customer ... designs. • Work closely with architecture and RTL designers on verifying the functionality ...
CPU CDC/RDC/STA Engineer
$184K - $324K/yr
At Apple, new ideas have a way of becoming extraordinary products, services, and customer ... CPU designs • Working with RTL and DV teams to recommend System Verilog assertions needed to ...
CPU CDC/RDC/STA Engineer
$184K - $324K/yr
At Apple, new ideas have a way of becoming extraordinary products, services, and customer ... CPU designs • Working with RTL and DV teams to recommend System Verilog assertions needed to ...
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Full-time
Medical, Retirement, PTO
Re-posted 27 days ago
Intel rating
8.7
Based on 147 frontline employees who took The Breakroom Quiz
18th of 159 rated electronics manufacturers
Job description
Intel's AI SoC organization is driving innovation in next-generation ASICs for AI applications across edge and cloud. As a Senior Formal Verification Engineer, you will play a critical role in ensuring the functional correctness of complex digital designs using advanced formal methods. This position offers the opportunity to work on cutting-edge technology and shape verification strategies for AI SoCs.
Key Responsibilities
- Own formal verification strategy and execution for complex SoC IP blocks and subsystems.
- Develop and maintain formal verification environments using SystemVerilog Assertions (SVA) and industry-standard formal tools.
- Write and review formal properties, constraints, and coverage goals to achieve exhaustive verification.
- Collaborate with design and simulation teams to identify corner cases and complement dynamic verification.
- Drive formal sign-off, including convergence analysis and coverage closure.
- Contribute to pre-silicon verification, chip bring-up, and post-silicon debug support.
- Mentor junior engineers and establish best practices for formal verification methodology
Additional Responsibilities
- Define and develop scalable, reusable verification plans for block, subsystem, and SoC levels.
- Execute verification plans and run emulation and system simulation models to validate design, analyze power/performance, and uncover bugs.
- Debug and root-cause issues in the presilicon environment; implement corrective measures.
- Collaborate with architects, RTL developers, and physical design teams to improve verification of complex features.
- Document test plans and lead technical reviews with design and architecture teams.
- Incorporate and execute security verification activities within regression and debug tests.
- Maintain and enhance existing functional verification infrastructure and methodology.
- Apply learnings from post-silicon validation to improve coverage and quality for future products.
Minimum Qualifications
Basic Qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science with 10+ years of related experience.
7+ years of experience in ASIC/SoC verification with at least 3+ years focused on formal verification.
Preferred Qualifications
Expertise in formal verification methodologies and tools (e.g., JasperGold, VC Formal, Questa Formal).
Strong knowledge of System Verilog Assertions (SVA) and property-based verification.
Deep understanding of digital design concepts, clock domain crossings, and low-power design techniques.
Familiarity with UVM-based simulation environments and how formal complements dynamic verification.
Scripting skills (Python, TCL, Perl) for automation and flow optimization.
Ability to lead projects, work cross-functionally, and deliver under tight schedules.
Strong analytical skills, attention to detail, and a collaborative mindset.
Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $220,920.00-311,890.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.About Intel
Sourced by ZipRecruiter
Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth
Industry
Manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1968