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60 Astera Labs Application Security Engineer Jobs Hiring Near You

Astera Labs

Senior ATE Test Engineer

San Jose, CA · On-site

$135K - $170K/yr

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity ... Role Overview We are looking for Senior ATE Test Engineers with proven experience in developing and ...

Astera Labs

Manager, ATE Test Engineering

San Jose, CA · On-site

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity ... Role Overview Astera Labs is seeking a Manager, ATE Test Engineering to lead our Test engineering ...

Astera Labs

Principal Optical Assembly Engineer

San Jose, CA · On-site

$185K - $240K/yr

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity ... About the Role Astera Labs is seeking a Principal Optical Assembly Engineer to drive development of ...

Astera Labs

Principal Digital Design Engineer

San Jose, CA · On-site

$185K - $230K/yr

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity ... Role Overview Join Astera Labs as a Principal Digital Design Engineer to architect and implement ...

Astera Labs

Performance Engineer

San Jose, CA · On-site

San Jose, CA (On-site) Role Overview Astera Labs is a hyper-growth connectivity company enabling ... application development and issue resolution. * Cross-Functional Impact & Innovation * Partner ...

Astera Labs

Product Tech Lead

San Jose, CA · On-site

$160K - $200K/yr

Astera Labs is hiring a Tech Lead Design Engineer to help architect and deliver the connectivity silicon powering the world's largest AI clusters. You'll own design execution on complex blocks across ...

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Senior ATE Test Engineer

Astera Labs

San Jose, CA • On-site

$135K - $170K/yr

Full-time

Posted 5 days ago

Job description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Role Overview
We are looking for Senior ATE Test Engineers with proven experience in developing and supporting complex mixed-signal silicon SoC products to lead ATE Test solutions. The ideal candidate will develop and oversee SoC test strategy, interact with manufacturing partners, define, and implement ATE programs and own the product from design, initial samples all the way through high volume production ramp. The candidate should have working knowledge of communication/interface protocols such as PCI-Express (Gen-4/5/6), Ethernet, Infiniband, DDR, NVMe, USB, etc. This is an opportunity to contribute hands-on technical expertise within Astera Labs' hyper-growth connectivity business and help deliver purpose-built solutions that scale with the demands of rack-scale AI systems.
Basic Qualifications
  • Strong academic and technical background in electrical engineering. At minimum, a Bachelor's in EE is required, and a Master's is preferred.
  • ≥2 year experience releasing complex SoC/silicon products to high volume manufacturing.
  • Working knowledge of high-speed protocols like PCIe, Ethernet, Infiniband, DDR, NVMe, USB, etc.
  • Professional attitude with ability to execute on multiple tasks with minimal supervision.
  • Strong team player with good communication skills to work alongside a team of high caliber engineers.
  • Entrepreneurial, open-mind behavior and can-do attitude.

Required Experience
  • Hands-on experience with high-speed mixed signal SoC test program/hardware development on multiple high-speed test platforms.
  • Collaboration with design team to define test strategy, create and own test plan.
  • Tester platform selection, design, and development of ATE hardware for wafer sort and final test.
  • Familiar with high-speed load board design techniques.
  • Proven track record of implementing ATE patterns to optimize tester resources and minimize ATE test time while maintaining product quality.
  • Strong knowledge and development of DFT techniques implemented in silicon that provide maximum defect and parametric device coverage - SCAN, MEMBIST, SerDes and other functional tests.
  • Skilled in control interfaces - I2C, I3C, SPI, MDIO, JTAG etc.
  • Expertise in production test of high speed SerDes operating at 16Gbps and higher.
  • Skilled in ATE programming, silicon/ATE bring-up, bench-ATE correlation and debug.
  • Experience with lab equipment including protocol analyzers and oscilloscopes.
  • Experience with using Advantest 93k ATE platform.
  • Proficiency in, at least, one modern programming language such as C/C++, Python.

Preferred Experience
  • Fluent in data processing using high level programming languages.
  • Experience in running External loopback at wafer sort.
  • Familiarity with modern databases

Salary range is $135,500 to $170,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

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