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Yield Enhancement Engineer Jobs (NOW HIRING)

onsemi

SiC Yield Enhancement Engineer

Livonia, NY

The SiC Yield Enhancement Senior Engineer is responsible for improving SiC manufacturing yield, solving process and defect issues, and supporting stable production ramp-up. The role requires hands-on ...

TSMC

Sr. Yield Enhancement Engineer

Camas, WA · On-site

$92K - $124K/yr

As a Yield Enhancement (Defect) Engineer, this position will be working within the PIE department in a dynamic and fast paced environment where sustain semiconductor manufacturing line stability is a ...

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How much do yield enhancement engineer jobs pay per year?

As of Jun 7, 2026, the average yearly pay for yield enhancement engineer in the United States is $89,183.00, according to ZipRecruiter salary data. Most workers in this role earn between $66,500.00 and $109,000.00 per year, depending on experience, location, and employer.

What is a Yield Enhancement Engineer job?

A Yield Enhancement Engineer is responsible for improving semiconductor manufacturing yield by identifying and reducing defects in the fabrication process. They analyze data, conduct failure analysis, and work with process engineers to implement corrective actions. Their role involves using statistical tools, defect inspection systems, and cleanroom equipment to enhance production efficiency. They collaborate with cross-functional teams to optimize processes and improve overall product quality.

What are the key skills and qualifications needed to thrive in the Yield Enhancement Engineer position, and why are they important?

To thrive as a Yield Enhancement Engineer, you need a solid background in materials science, semiconductor physics, data analysis, and process engineering, generally supported by a relevant engineering degree. Experience with failure analysis tools, statistical process control (SPC) software, and data visualization platforms like JMP or Minitab is highly beneficial. Strong problem-solving abilities, effective communication, and a collaborative attitude distinguish top performers in this role. These competencies are vital for efficiently identifying manufacturing issues, driving process improvements, and working cross-functionally to maximize production yields.

What are some common challenges Yield Enhancement Engineers face, and how do they address them?

Yield Enhancement Engineers often encounter challenges such as identifying the root causes of yield loss in complex semiconductor manufacturing processes and implementing sustainable improvement solutions. These challenges require a mix of analytical skills, the ability to interpret large datasets, and close collaboration with process engineers, equipment technicians, and quality teams. To overcome these hurdles, they must proactively investigate process variations, conduct thorough failure analyses, and stay current with technological advancements. Effective communication and project management skills also help them coordinate cross-functional initiatives and drive continuous improvement. Overall, overcoming these challenges is essential to reducing production costs and maintaining high product quality.

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Yield Enhancement Engineer jobs near you
Senior Yield Enhancement Engineer

Senior Yield Enhancement Engineer

Cerebras Systems

Sunnyvale, CA

$175K - $250K/yr

Other

Posted 20 days ago

Job description

The Role: Senior Yield Enhancement Engineer 

We are seeking a highly experienced Senior VLSI Product and Test Engineer with 7+ years of relevant experience in Semiconductor Testing/Failure Analysis/Yield Enhancement. The successful candidate will look at ATE datalogs, understand the defects in detail, disposition wafers based on ATE data and drive FA/Yield enhancement using physical/optical inspection techniques used in FA. 

Suitable candidate will have depth in testing, characterization of silicon defects, failure modes, and experience delivering end-to-end solutions working closely with teams across chip design, fabrication, validation, production, and manufacturing. 

Key Responsibilities  

  • Analyze ATE data logs, Shmoo plots, parametric characterization data, and spatial wafer defect patterns. 
  • Develop failure analysis tools using optical, photo emission, and laser-based defect localization techniques specific to Cerebras hardware. 
  • Develop and execute FIB (Focused Ion Beam) edit plans for Silicon root cause validation. 
  • Communicating with OSATs and Fab to drive production testing in HVM environment. 
  • Understand DFT strategies including hierarchical scan chains, distributed BIST, SRAM test methodologies, and perform diagnosis on ATE data. 
  • Collaborate closely with DFT engineers, silicon architects, designers, performance teams, and software engineers to enhance overall testability and yield 
  • Refine test programs across di/dt behavior, voltage-frequency characterization space, current limits, and thermal constraints based on ATE logs and disposition learnings. 
  • Understand and write Python scripts and UNIX environment. 

Required Skills & Qualifications 

  • Bachelor's or Master's degree in Electrical Engineering / Computer Engineering, or related field 
  • 7+ years of hands-on experience in semiconductor test engineering/ FA/ Yield Enhancement. 
  • Hands-on experience with lab debug tools including Oscilloscopes (high-speed probing and signal integrity), wafer probe stations, probe cards, Keyence/Optical inspection systems, and advanced imaging techniques. 
  • Failure analysis (FA) expertise including use of optical probing tools, physical inspection workflows, and correlation of electrical failures to physical defects. 
  • Strong capability to read and understand Digital CMOS layouts, power grids, routing structures and SRAM arrays. 
  • ATE test program debugging, and yield improvement experience. 
  • Good interpersonal skills with the ability and desire to work as a standout colleague and problem solver. 
  • Proven track record of working cross-functionally, learning fast, and driving issues to closure 
  • Working knowledge of git repositories, GitHub, git actions/Jenkins, merge and release flows to streamline test and release 
  • Proficiency in programming languages: Python, C/C++, Perl for large-scale data analysis 

Preferred Skills 

  • Develop fault isolation techniques using OBIRCH/IREM/LADA optical techniques. 
  • Experience with advanced test data analysis tools and machine learning techniques for yield optimization. 
  • Familiarity with advanced packaging technologies for wafer-scale systems (TSV, advanced interconnects). 
  • Familiarity with in-line testing and diagnostics using CPU memory and execution with self-checking. 
  • Knowledge of chip defect profiles and mitigation strategies across manufacturing steps. 

Location 

  • North America based. Sunnyvale, up to 20% travel may be needed. 

The base salary range for this position is $175,000 to $250,000 annually.  Actual compensation may include bonus and equity, and will be determined based on factors such as experience, skills, and qualifications.

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