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Work From Home Analog Design Engineer Jobs (NOW HIRING)

IC Enable

RTL Design Engineer

Richardson, TX · On-site +1

$122K/yr

Work closely with analog/mixed-signal, physical design, firmware, product, and customer-facing ... ranging from innovative startups to Fortune 50 companies. Our expertise spans high-reliability ...

Next Step Systems

FPGA Engineer - Work From Home

Chicago, IL · On-site +1

$133K - $172K/yr

Chicago IL Jobs, FPGA Engineer, FPGA, VHDL, Verilog, Vivado, ModelSim, ISE Design, Secure IP, IP ... Work From Home, Financial, Trading, Chicago Recruiters, Information Technology Jobs, IT Jobs, ...

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Work From Home Analog Design Engineer information

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How much do work from home analog design engineer jobs pay per year?

As of Aug 15, 2026, the average yearly pay for work from home analog design engineer in the United States is $186,238.00, according to ZipRecruiter salary data. Most workers in this role earn between $202,000.00 and $202,000.00 per year, depending on experience, location, and employer.

Are work from home analog design engineers in demand?

Work from home analog design engineers are in demand due to the increasing need for remote work options and the ongoing growth of electronics and semiconductor industries. Skills in circuit simulation tools and a strong understanding of analog circuitry enhance employability in this flexible work environment.

What is a work from home analog design engineer?

A Work From Home Analog Design Engineer designs, develops, and tests analog circuits and systems remotely. They work on components such as amplifiers, power management circuits, and signal processing systems, often using simulation tools and EDA software. Communication with teams occurs via email, video calls, and collaboration platforms. This role requires strong knowledge of circuit design, layout, testing, and troubleshooting. It offers flexibility while demanding self-discipline and effective remote collaboration skills.

What are the primary challenges of working remotely as an analog design engineer, and how are they addressed?

One of the main challenges for remote Analog Design Engineers is maintaining clear communication and seamless collaboration with team members, especially when coordinating on complex designs and reviews. Employers typically address this by providing robust communication platforms, project management tools, and remote access to design software and lab resources. Regular virtual meetings, scheduled design reviews, and clear documentation practices also help bridge the distance. Staying proactive and organized is important to ensure timely project milestones and effective issue resolution.

What are the key skills and qualifications needed to thrive as a work from home analog design engineer?

A Work From Home Analog Design Engineer should have a strong grasp of analog circuit theory, IC design, and simulation, typically backed by a degree in electrical engineering or a related field. Familiarity with EDA tools like Cadence, SPICE simulators, and experience with layout and verification environments are highly valuable, as is a solid understanding of semiconductor technology. Outstanding communication, self-motivation, and the ability to collaborate remotely with cross-functional teams help professionals excel in this position. These competencies ensure successful design, effective teamwork, and reliable project delivery in a remote engineering environment.

Can you work from home as a work from home analog design engineer?

Work from home as an analog design engineer is possible, especially for tasks involving circuit simulation, schematic design, and testing that can be done remotely with the right tools and secure access. However, some roles may require on-site presence for hardware testing, collaboration, or equipment setup. The feasibility depends on the company's policies and the specific responsibilities of the position.
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Work From Home Analog Design Engineer jobs near you
Infographic showing various Work From Home Analog Design Engineer job openings in the United States as of August 2026, with employment types broken down into 1% As Needed, 78% Full Time, 17% Part Time, and 4% Contract. Highlights an 93% Physical, 2% Hybrid, and 5% Remote job distribution, with an average salary of $186,238 per year, or $89.5 per hour.

High-Speed Analog Layout Design Engineer

Celero Communications, Inc.

Austin, TX • On-site, Remote

$200K/yr

Full-time

Posted 3 days ago

New

Job description

Senior to Principal High-Speed Analog Layout Design Engineer roles
Locations: Irvine, CA or San Jose, CA or remote + travel to Irvine, CA
About the Role
Celero Communication Inc. is an exciting and fast-growing start-up in the semiconductor industry, pushing boundaries with innovative technologies that power the world’s most advanced AI and data center infrastructure. As we scale rapidly, we are looking for a driven and resourceful High-Speed Analog Layout Engineer to be the backbone of our daily operations and a key partner in shaping our company culture.
 
We are seeking a Principal/Senior Analog Layout Engineer to drive the layout design of complex analog and mixed-signal IP blocks that are at the heart of our advanced optical communication systems. As a key member of the Analog & Mixed-Signal (AMS) design team, you will lead layout development of critical blocks such as ADCs, DACs, PLLs, and other high-performance analog/mixed-signal circuits. You will interface closely with circuit designers, CAD/PDK teams, and other layout engineers to ensure first-pass silicon success. This is a hands-on technical role ideal for someone who thrives in a fast-paced environment and enjoys mentoring others while contributing directly to cutting-edge chip development.
 
Key Responsibilities
• Lead and own the physical layout design of complex analog/mixed-signal macros (e.g., ADCs, DACs, PLLs), from floor planning through final verification
• Collaborate closely with schematic designers to create optimal layout solutions considering performance, matching, symmetry, and reliability
• Mentor and guide junior layout engineers/contractors across multiple time zones, enforcing best practices in layout design and verification
• Perform and debug full hierarchy LVS, DRC, PERC, ERC, and other signoff checks using industry-standard tools (Pegasus, Calibre, etc.)
• Contribute to chip-level planning including top-level floor planning, block integration, power grid implementation, and signal routing
• Participate in layout design reviews and provide technical leadership for layout quality, verification completeness, and schedule adherence
• Support automation initiatives through scripting and tool customization (SKILL, TCL, Python is a plus)
 
Required Qualifications
• Minimum 10+ years of hands-on analog/mixed-signal layout design experience in advanced CMOS/FinFET technologies
• Proven track record of top level integration IP layout macros and preparing IPs for handoff to Physical Design
• Proven leadership in owning major IP layout macros or full-chip-level layout at FinFET nodes (TSMC preferred)
• At least 1 year of experience with TSMC FinFET process nodes (N3, N5, N7, or N16)
• Deep understanding of device physics, layout-dependent effects (LOD, WPE, OSE, LDE, etc.), and their impact on circuit performance
• Strong expertise in layout best practices for device matching, noise isolation, ESD protection, symmetry, and parasitic minimization
• Proficiency in floor planning, hierarchical block integration, routing strategy, and power/ground grid design
• Expertise with Cadence Virtuoso, Calibre, Pegasus, and other layout and verification tools
• Familiarity with layout verification flows, including LVS, DRC, PERC, Density, DFM, ERC, and Antenna rules
• Experience working in collaborative environments with international and remote teams
• Strong documentation and communication skills with the ability to clearly present layout trade-offs and status to cross-functional teams
• Experience using revision control systems for layout design management
 
Preferred Qualifications
• Exposure to optical or high-speed analog interfaces is a strong plus
• Working knowledge of SKILL, TCL, or Python for layout automation or design flow optimization
• Proven ability to collaborate with international teams (U.S., Canada, Argentina)
• Strong organizational skills with high attention to detail and follow-through
• Ability to multi-task and prioritize in a fast-paced, dynamic environment
• Proactive, eager-to-learn mindset with excellent problem-solving skills
 
What We Offer
• The chance to play a foundational role at a high-growth semiconductor start-up
• Exposure to a wide variety of cross functional teams
• A collaborative, international team culture where ideas and initiative are valued
• The opportunity to grow alongside Celero as we scale and shape the future of our industry
• A foundational role at a fast-growing semiconductor start-up shaping the future of AI and data center connectivity
 
Note: Since we have several roles available, candidate job level will be evaluated during interview process.