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Uvm Extension Jobs (NOW HIRING)

Xoriant Corporation

Design Verification Engineer

Austin, TX · Hybrid

$134K - $164K/yr

Design Verification Engineer #368877 Duration: 12+ months (Possible Extension-Long Term Project ... Develop Scalable SystemVerilog/UVM testbenches for unit level and/or Cluster level verification.

Tenstorrent

$154K - $188K/yr

Develop UVM, assembly, C/C++ stimulus, and C++ functional models for RISC-V extensions and un-core components such as APIC and IOMMU. * Debug regressions, close coverage, and improve core, cluster ...

Tenstorrent

$100K - $500K/yr

Develop and execute architecture-focused verification content using UVM, assembly, C/C++, directed ... Develop and debug functional models of RISC-V extensions and CPU-adjacent components relevant to ...

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How much do uvm extension jobs pay per year?

As of Jun 6, 2026, the average yearly pay for uvm extension in the United States is $154,823.00, according to ZipRecruiter salary data. Most workers in this role earn between $139,000.00 and $170,000.00 per year, depending on experience, location, and employer.

What is a UVM Extension job?

A UVM Extension job typically involves supporting and implementing Universal Verification Methodology (UVM) in semiconductor verification. Engineers in this role develop testbenches, write verification IPs, and ensure the functional correctness of complex designs. They work with SystemVerilog and simulation tools to create scalable and reusable verification environments. This role is crucial in validating ASIC and FPGA designs before fabrication.

What are the primary responsibilities of a UVM Extension professional on a daily basis?

A UVM Extension professional typically spends their days developing and delivering educational programs, conducting outreach to local communities, and collaborating with faculty or specialists to apply research findings in practical settings. Responsibilities may include organizing workshops for farmers or landowners, providing technical assistance, and evaluating program outcomes to ensure they meet community needs. This role often involves traveling within the region, working with diverse audiences, and staying current with industry advances to offer relevant, timely guidance. Teamwork is essential, as you’ll frequently partner with other extension staff, university departments, and external organizations to maximize program impact.

What are the key skills and qualifications needed to thrive in the Uvm Extension position, and why are they important?

To thrive in a UVM Extension position, you need a strong background in agriculture, community education, or environmental science, supported by a relevant degree. Familiarity with data collection tools, outreach platforms, and educational software is often necessary, as is experience with program management or extension certifications. Outstanding interpersonal skills, public speaking ability, and adaptability make someone stand out in this public-facing, community-oriented role. These skills and qualities are critical for developing effective programs, building lasting community partnerships, and translating research into real-world solutions for local stakeholders.

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What cities are hiring for Uvm Extension jobs? Cities with the most Uvm Extension job openings:
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Uvm Extension jobs near you
Infographic showing various Uvm Extension job openings in the United States as of May 2026, with employment types broken down into 33% Part Time, and 67% Contract. Highlights an 100% In-person job distribution, with an average salary of $154,823 per year, or $74.4 per hour.
Design Verification Engineer

Design Verification Engineer

Xoriant Corporation

Austin, TX • Hybrid

$134K - $164K/yr

Other

Posted 8 days ago

Job description

Job Title: Design Verification Engineer #368877

Duration: 12+ months (Possible Extension-Long Term Project)

Location: San Jose, CA / Austin, TX (Hybrid-3 Days onsite)

Description

  • As a Design Verification Engineer you will contribute to the functional verification of GPU Subsystems such as Shader, Texture, and Memory Systems.

Responsibilities

  • Triage regression failures and make testbench updates
  • Debug functional errors in RTL model using simulation and debug tools.
  • Maintain efficient and clean regression status
  • Develop Scalable SystemVerilog/UVM testbenches for unit level and/or Cluster level verification.
  • Review Architecture and Micro-Architecture specifications.
  • Closely work with Architects and RTL designers.
  • Define, maintain and execute unit level and/or Cluster level verification testplans.
  • Generate and run Testcases on logic simulation models.
  • Code Functional coverage models and System Verilog assertions.
  • Drive Functional Coverage and Code coverage to closure.
  • Integrate C++ reference model into Scoreboards

Requirements

  • 5-15 year s industry experience in a design verification role.
  • Proficient in System Verilog/UVM/OVM, OOP/C++
  • Knowledge of GPU, experience with Shader, Texture, or Memory System a plus
  • Experience with code coverage and functional coverage driven verification methodology.
  • Experience in creating, running and debugging of SystemVerilog/UVM constraint-random Testbench.
  • Excellent working knowledge of scripting languages such as Python or Perl.
  • Understanding of micro-architecture, logic design, FSMs, arithmetic datapath pipelines.
  • Strong functional verification experience including Test planning, Testbench Architecture, Test/Coverage Model/Assertion Development.
  • Strong debugging skills
  • Strong programming skills with good understanding of algorithms and data structures
  • Good verbal and written communication skills.

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