Trainee Computer Chip Engineer Jobs in California

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Science Engineering, or equivalent practical experience.
• 5 years of experience working with Computer-aided design (CAD).
• Experience with Python, AI algorithms, front-end development, object-oriented analysis and design, chip design, and data structures.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Science Engineering, or equivalent practical experience.
• Experience in developing EDA tools for chip design flows including industry standard EDA tools.
• Experience in extraction of hardware-design/software parameters including quality metrics, performance monitoring, dashboards, and analyzing-trends.
• Experience with frontend design (including web-design) technologies such as Angular, TypeScript, and databases.

About the job
In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As a Senior Engineer within Google's silicon team, you will help deliver products that have a substantive impact on the Technical Infrastructure that powers Google. You will provide leadership to a group of hardware engineers in a fluid environment with a focus on infrastructure for chip design. You will also lead the technical projects from the concept/planning stage through execution and closure.
In this role, you will help your team deliver designs that work for the first time in a number of different application areas. Leveraging your technical and leadership expertise, you will lead the chip design process improvement projects in multiple areas of expertise. You will architect and develop novel, full-stack software systems that redefine the landscape of chip design. You will stand at the intersection of software and silicon engineering, utilizing AI and Machine Learning to automate high-complexity tasks, predict critical performance bottlenecks, and hyper-optimize the development lifecycle of Google Custom Silicon.
The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $174000 - $253000 (USD) 15% bonus target equity benefits
Learn more about benefits at Google .
Responsibilities

• Architect, develop, and execute comprehensive EDA CAD tool flows spanning the entire chip design spectrum.
• Research, develop, and deploy AI/Machine Learning models within our CAD flows to enhance predictive modeling, automate routing, and provide intelligent design insights.
• Design and implement both the frontend and backend of novel software systems to streamline complex engineering workflows and provide an exceptional user experience.
• Partner closely with chip design teams to implement methodologies that directly optimize PPA (Power, Performance, and Area) and TAT (Turn Around Time) for design cycles.
• Lead technical evaluations of emerging EDA CAD tools and provide data-driven recommendations for adoption.

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