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Tpu Jobs (NOW HIRING)

Socket.dev

Senior RTL Design Engineer, TPU

Sunnyvale, CA · On-site

$163 - $236/hr

You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries ...

Google

TPU RTL Design Engineer

Sunnyvale, CA · On-site

$159K/yr

You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries ...

Google

RTL Design Engineer, TPU

Sunnyvale, CA · On-site

You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries ...

Google

TPU SoC Design Engineer, Google Cloud

Sunnyvale, CA · On-site

$159K/yr

You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries ...

Google

ASIC Design Verification Engineer, TPU

Sunnyvale, CA · On-site

$159K - $194K/yr

You will have an opportunity to drive TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing ...

Google

TPU PCIe RTL Design Engineer

Sunnyvale, CA · On-site

You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries ...

Google

Senior RTL Design Engineer, TPU

Sunnyvale, CA · On-site

You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries ...

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How much do tpu jobs pay per year?

As of Aug 17, 2026, the average yearly pay for tpu in the United States is $88,611.00, according to ZipRecruiter salary data. Most workers in this role earn between $66,000.00 and $112,000.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive in the TPU position, and why are they important?

To thrive as a TPO (Technical Project Updater), you need strong project management abilities, technical knowledge relevant to the industry, and keen attention to detail, typically gained through a bachelor's degree in a related field and experience managing technical documentation. Familiarity with project management software like Jira or Asana, and proficiency in updating technical databases and tracking systems, are important. Excellent communication, organization, and time management skills help TPOs manage multiple updates and cross-team collaboration efficiently. These competencies are vital to ensure project statuses are accurately tracked and communicated, leading to better coordination and timely project delivery.

What is a TPU?

A TPU (Tensor Processing Unit) job typically involves working with specialized hardware accelerators designed to enhance machine learning workloads, particularly deep learning models. These jobs may include roles in AI research, model optimization, and deploying machine learning applications at scale. Professionals in TPU-related roles often have expertise in TensorFlow, neural networks, and high-performance computing.

What are the typical daily responsibilities of a TPU?

As a TPO, your daily tasks usually involve updating the progress of ongoing technical projects, maintaining documentation systems, and ensuring all stakeholders are informed of key developments. You will collaborate closely with engineers, project managers, and other team members to gather data and report on milestones or issues. Additionally, you may be responsible for organizing and participating in status meetings, helping to identify roadblocks, and keeping workflow tools up to date. The role requires excellent multitasking and organizational skills to manage multiple projects simultaneously while delivering accurate information in a fast-paced environment.

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Tpu jobs near you
Infographic showing various Tpu job openings in the United States as of August 2026, with employment types broken down into 98% Full Time, 1% Part Time, and 1% Contract. Highlights an 93% Physical, 1% Hybrid, and 6% Remote job distribution, with an average salary of $88,611 per year, or $42.6 per hour.

Senior RTL Design Engineer, TPU

Socket.dev

Sunnyvale, CA • On-site

$163 - $236/hr

Other

Posted 6 days ago

Job description

Minimum qualifications:
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 8 years of experience in ASIC design.
  • Experience with SystemVerilog/RTL coding.
  • Experience with scripting languages (e.g., Tcl, Python or Perl).
Preferred qualifications:
  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  • Experience interacting with software, system hardware, and other cross-functional teams.
  • Experience with chip management, clocking, reset, and peripherals like I2C, SPI, UART, etc.
  • Understanding of digital design fundamentals, including synchronous and asynchronous logic, state machines and bus protocols.
About the job:

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

In this role, you will join a team working on SoC-level RTL design for our data center accelerators. You will design RTL Intellectual Property (IP) with the focus on management and control subsystem, also participate in developing infrastructure and methodology that form the foundation of our SoCs (i.e., clocking, reset, error handling, debug, chip management and SOC chassis etc.). You will build a global understanding of how our accelerators are built from concept to production. This is a highly cross-functional role that will require you to coordinate and co-design with our software and system hardware counterparts. You will utilize, a background in RTL design, and the ability to lead to multi-faceted efforts involving many stakeholders.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google.

Responsibilities:
  • Work separately to create and review management and control subsystem's design microarchitecture specifications.
  • Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines.
  • Work with architecture and power teams to evaluate features and their impact.
  • Work with design validation (DV) teams to create test plans to verify, and debug design RTL.
  • Work with physical design teams to ensure design meets physical requirements and timing closure.
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