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Temporary Asic Rtl Design Engineer Jobs in New York

Redolent, Inc.

US_East | Network Design Engineer_L3

NJ · On-site

$206K/yr

... RTL coding including state machines, adders, multipliers, combinatorial logic, etc • Good ... Analog/Mixed-Signal (AMS) Design Verification (DV) Engineer * Local Skills : Julie Skidmore

New

Virtusa

Vice President

New York, NY

SmartSoC combines deep silicon engineering expertise with Virtusa's global delivery capabilities ... full ASIC and SoC development lifecycle - from architecture definition and RTL design through ...

Redolent, Inc.

US_West | Network Design Engineer_L3

NJ · On-site

$206K/yr

San Jose, CA 100% Onsite Qualifications • Good knowledge of System-Verilog RTL coding including ... Mixed-Signal Design Verification Engineer * Local Skills : Julie Skidmore * Languages Required:

New

Virtusa Corporation

Vice President

New York, NY · On-site

SmartSoC combines deep silicon engineering expertise with Virtusa's global delivery capabilities ... full ASIC and SoC development lifecycle - from architecture definition and RTL design through ...

Microchip Technology

Engineer II - Design

Hauppauge, NY · On-site

As part of our seasoned ASIC design team, you will work on processor based products that go into ... Programming languages like C, Python, Perl, TCL. Self-starter and team player attitude Willingness ...

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Temporary Asic Rtl Design Engineer information

What is the difference between Temporary Asic Rtl Design Engineer vs Temporary FPGA Design Engineer?

AspectTemporary Asic Rtl Design EngineerTemporary FPGA Design Engineer
Primary FocusDesigning RTL code for ASIC chipsDesigning FPGA logic and configurations
Skills & CertificationsVerilog/VHDL, ASIC design flow, simulation toolsVerilog/VHDL, FPGA development tools, synthesis
Work EnvironmentSemiconductor companies, ASIC design teamsFPGA development labs, prototyping environments
Industry UsageUsed in high-volume chip manufacturingUsed for prototyping, testing, and low-volume products

Both roles involve RTL design using Verilog or VHDL, but the Temporary Asic Rtl Design Engineer focuses on ASIC chip development, while the Temporary FPGA Design Engineer specializes in FPGA-based prototyping and testing. The choice depends on whether the project aims for mass production or flexible, rapid development.

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Temporary Asic Rtl Design Engineer jobs near you

Design Verification (DV) Engineer - 2027 Grads

Hudson River Trading

New York, NY • On-site

$148K - $181K/yr

Full-time

Posted 5 days ago

Key responsibilities

  • Create testbenches and tests for hardware platforms using a hybrid open-source/proprietary environment

  • Write detailed verification plans and quickly root-cause RTL bugs

  • Collaborate with designers for rapid project bringup and debugging of existing designs

Job description

The Hardware team at Hudson River Trading (HRT) creates high performance compute engines using FPGA and ASIC technologies to drive low latency trading decisions on global markets. We build custom solutions across the spectrum of speed and smarts: from bespoke circuits to world-class machine learning accelerators.
These high performance designs require even higher performance verification. We are looking for Design Verification (DV) engineers who are passionate about writing testbenches and building verification environments to exercise complex HDL. You are excited about exploring the EDA landscape and want to be part of a team actively working to rethink, redesign, and surpass the status quo. For example, members of our team are active maintainers of popular open source projects such as Slang, Verilator, and Cocotb.
Design verification is part of an innovative, growing team at HRT which is integral to the success of our trading. You can expect to always be challenged by the ever-changing financial markets as you work to ensure correctness and robustness of our critical hardware in an extremely fast-paced, real-time environment. No financial experience is necessary.
Responsibilities
  • Creating testbenches and tests for our hardware platform, leveraging a hybrid open-source/proprietary, highly flexible environment
  • Writing detailed verification plans
  • Quickly root-cause RTL bugs
  • Collaborating directly with designers for rapid bringup of new projects and debugging of existing designs
  • Managing test suites and continuous integration infrastructure
  • Developing and improving open-source and internal tools

Qualifications
  • Superb debugging and analytical skills
  • Experience with RTL functional verification
  • Proficiency in Python
  • Comfortable in a Linux environment
  • Familiarity with Cocotb preferred
  • C++ experience is a plus
  • A bachelor's degree in computer engineering, computer science or a related field

We do not allow multiple applications. Please apply to the ONE role you are most interested in and we will consider you for all open positions when reviewing your application.
The estimated base salary range for this position is 300,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience. This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package.
Culture
Hudson River Trading (HRT) brings a scientific approach to trading financial products. We have built one of the world's most sophisticated computing environments for research and development. Our researchers are at the forefront of innovation in the world of algorithmic trading.
At HRT we welcome a variety of expertise: mathematics and computer science, physics and engineering, media and tech. We're a community of self-starters who are motivated by the excitement of being at the cutting edge of automation in every part of our organization-from trading, to business operations, to recruiting and beyond. We value openness and transparency, and celebrate great ideas from HRT veterans and new hires alike. At HRT we're friends and colleagues - whether we are sharing a meal, playing the latest board game, or writing elegant code. We embrace a culture of togetherness that extends far beyond the walls of our office.
Feel like you belong at HRT? Our goal is to find the best people and bring them together to do great work in a place where everyone is valued. HRT is proud of our diverse staff; we have offices all over the globe and benefit from our varied and unique perspectives. HRT is an equal opportunity employer; so whoever you are we'd love to get to know you.
Please be advised: Use of AI tools during interviews or assessments is strictly prohibited, unless otherwise instructed or agreed upon. We employ various methods to evaluate the authenticity of candidate responses. If we determine that AI assistance was used during any stage of the hiring process, we reserve the right to immediately disqualify your candidacy or rescind any job offers extended.

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