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Temporary Asic Design Engineer Jobs in Vermont (NOW HIRING)

TEKsystems

Software Engineer

East Thetford, VT · Remote

$55 - $65/hr

Design and build RESTful APIs and web services * Support modernization of legacy applications into ... If eligible, the benefits available for this temporary role may include the following: • Medical ...

Dellfor Technologies

senior java developer

Vernon, VT

$57.50 - $73.25/hr

And we do it every single day - for both temporary and permanent assignments and across virtually ... Involved in design sessions, did analysis on requirements, participated in task break downs and ...

Dellfor Technologies

senior .net developer

Underhill, VT · On-site

$56.50 - $72/hr

As a full stack engineer your contribution will have a direct impact on our customer experience and ... Strong knowledge of SOA in terms of design and implementation. * At least 5+ years of developing ...

Dellfor Technologies

Java ATG Developer

Montpelier, VT

$60K/yr

And we do it every single day - for both temporary and permanent assignments and across virtually ... Experience with all phases of the Software Development Lifecycle, including system analysis, design ...

Listen Community Services

Retail Thrift Store Manager

VT · On-site

$48K - $58K/yr

... temporary workforce as needed). * Foster a positive, mission-aligned workplace culture rooted in ... Design and refresh merchandise displays to optimize sales and enhance customer experience.

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Temporary Asic Design Engineer information

What is the difference between Temporary Asic Design Engineer vs Temporary FPGA Design Engineer?

AspectTemporary Asic Design EngineerTemporary FPGA Design Engineer
Required SkillsASIC architecture, digital design, verification, HDL (Verilog/VHDL)FPGA development, HDL (Verilog/VHDL), prototyping
Work EnvironmentSemiconductor companies, chip design labsPrototyping labs, FPGA manufacturing facilities
Industry UsageIntegrated circuit manufacturing, consumer electronicsPrototyping, testing, and development projects

Temporary Asic Design Engineers focus on designing and verifying ASIC chips, often working in semiconductor companies. Temporary FPGA Design Engineers work on FPGA prototyping and testing, typically in research or development labs. Both roles require HDL skills but differ in their focus on chip fabrication versus flexible prototyping.

Are temporary ASIC design engineers in demand?

Temporary ASIC design engineers are in demand due to the ongoing need for specialized hardware development in industries like telecommunications, consumer electronics, and data centers. Skills in hardware description languages such as VHDL or Verilog and experience with FPGA prototyping can enhance job prospects in this field.

How much does a Temporary ASIC Design Engineer make?

A Temporary ASIC Design Engineer typically earns between $40 and $70 per hour, depending on experience, location, and the complexity of the projects. Compensation may also include benefits such as flexible schedules and exposure to advanced design tools like Verilog and FPGA environments.

Is a temporary ASIC design engineer design difficult?

Designing as an ASIC design engineer can be complex due to the need for specialized knowledge in digital logic, hardware description languages, and verification tools. The difficulty varies based on project scope, experience, and familiarity with industry standards, but it generally requires strong technical skills and attention to detail.

What are popular job titles related to Temporary Asic Design Engineer jobs in Vermont?

For Temporary Asic Design Engineer jobs in Vermont, the most frequently searched job titles are:

What job categories do people searching Temporary Asic Design Engineer jobs in Vermont look for?

The top searched job categories for Temporary Asic Design Engineer jobs in Vermont are:

What cities in Vermont are hiring for Temporary Asic Design Engineer jobs?

Cities in Vermont with the most Temporary Asic Design Engineer job openings:

Temporary Asic Design Engineer jobs near you
Infographic showing various Temporary Asic Design Engineer job openings in Vermont as of August 2026, with employment types broken down into 86% Full Time, 12% Part Time, and 2% Contract. Highlights an 81% Physical, 5% Hybrid, and 14% Remote job distribution.

Sr Physical Design Engineer (Synopsys Fusion / GF 12LP) - Remote - Full Time / Contract

Burlington, VT • On-site, Remote

Encore Semi, Inc.
Semiconductor and Electronic Component Manufacturing • 51 - 200 employees
Learn more about Encore Semi, Inc.external

$150K - $165K/yr

Full-time

Medical, Dental, Vision, Life, Retirement, PTO

This job post has expired 1 day ago. Applications are no longer accepted.

Job description

Sr Physical Design Engineer (Synopsys Fusion / GF 12LP) - Remote - Full Time / Contract
Full-time: Salary + Benefits + Bonuses / Contractor
Work Status: US Citizen or Lawful Permanent Resident.
We have an immediate need for an expert Physical Design Engineer to drive a high-speed design across the finish line. You will be working on a 1GHz AES hard macro targeted for the GlobalFoundries 12LP (12nm FinFET) process node. The design is nearly complete; your primary objective upon joining will be the final cleanup of 7 remaining DRC/ERC errors, completing fill insertion, and executing the final Calibre signoff checks for tape-out.
Core Technical Environment & Ongoing Responsibilities: Beyond this immediate milestone, you will take ownership of the RTL-to-GDSII flow for our next-generation SoCs, pushing the limits of Power, Performance, and Area (PPA).
  • Implementation: Execute block-level and top-level physical design (floorplanning, CTS, routing) using the Synopsys Fusion Design Platform (Fusion Compiler).
  • Timing & Signoff: Drive STA, parasitic extraction, and timing closure across multiple corners using PrimeTime and StarRC.
  • FinFET Optimization: Address 12nm FinFET challenges including advanced routing rules, EM/IR-drop analysis (Ansys RedHawk), and complex SDC constraint management.
  • Verification: Perform DRC, LVS, and antenna checks using Calibre and Synopsys IC Validator (ICV).
  • Automation: Maintain robust Tcl, Python, or Perl scripts to automate workflows.
Qualifications:
  • 10+ years of industry experience in ASIC physical design with successful tape-outs on advanced FinFET nodes (14nm/12nm/7nm).
  • Deep expertise in rapid DRC/LVS/ERC closure and final tape-out procedures.
  • Hands-on mastery of Synopsys Fusion Compiler (or ICC2) and PrimeTime.
  • Strong scripting skills (Tcl, Python, Bash).
  • Preferred: Direct experience with the GlobalFoundries 12LP/12LP+ node and Mentor Calibre.

The anticipated annual base salary for this position is between $150,000 to $165,000, which also includes a comprehensive benefits package.
Full-Time Benefits:
•15 days of PTO per calendar year
•10 paid Holidays per calendar year
•Comprehensive Medical Benefits: Company covers 80% of premiums for Employee and Dependents
•Dental & Vision: Company covers 50% of premiums for Employee and Dependents
•Voluntary Benefits: Life Insurance, FSA (Health and Dependent, Limited Purpose), HAS, and Gap Insurance
•Employee Assistant Program (EAP)
•401k - Traditional & Roth
•Life/AD&D and Long-Term Disability
•Tuition reimbursement
Equal Opportunity Policy Statement
Encore Semi, Inc. is an Equal Opportunity Employer that does not discriminate on the basis of actual or perceived race, religion, creed, color, age, sex, sexual orientation, gender, gender identity or expression, national origin, genetics, ancestry, marital status, civil union status, medical condition, disability (mental and physical), military and veteran status, pregnancy, childbirth and related medical conditions, or any other characteristic protected by applicable federal, state, or local laws and ordinances.
Encore Semi is also committed to compliance with all fair employment practices regarding citizenship and immigration status.
LinkedIn :: https://www.linkedin.com/in/rtl2gds/

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