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Temporary Asic Design Engineer Jobs in Williston, VT

Dellfor Technologies

senior .net developer

Underhill, VT

$56.50 - $72/hr

As a full stack engineer your contribution will have a direct impact on our customer experience and ... Strong knowledge of SOA in terms of design and implementation. * At least 5+ years of developing ...

All JobsAsic Design Engineer JobsTemporary Asic Design Engineer JobsTemporary Asic Design Engineer Jobs in Williston, VT

Temporary Asic Design Engineer information

See Williston, VT salary details

$97K

$154.9K

$208.3K

How much do temporary asic design engineer jobs pay per year?

As of Aug 18, 2026, the average yearly pay for temporary asic design engineer in Williston, VT is $154,912.00, according to ZipRecruiter salary data. Most workers in this role earn between $135,600.00 and $185,700.00 per year, depending on experience, location, and employer.

What is the difference between Temporary Asic Design Engineer vs Temporary FPGA Design Engineer?

AspectTemporary Asic Design EngineerTemporary FPGA Design Engineer
Required SkillsASIC architecture, digital design, verification, HDL (Verilog/VHDL)FPGA development, HDL (Verilog/VHDL), prototyping
Work EnvironmentSemiconductor companies, chip design labsPrototyping labs, FPGA manufacturing facilities
Industry UsageIntegrated circuit manufacturing, consumer electronicsPrototyping, testing, and development projects

Temporary Asic Design Engineers focus on designing and verifying ASIC chips, often working in semiconductor companies. Temporary FPGA Design Engineers work on FPGA prototyping and testing, typically in research or development labs. Both roles require HDL skills but differ in their focus on chip fabrication versus flexible prototyping.

Are temporary ASIC design engineers in demand?

Temporary ASIC design engineers are in demand due to the ongoing need for specialized hardware development in industries like telecommunications, consumer electronics, and data centers. Skills in hardware description languages such as VHDL or Verilog and experience with FPGA prototyping can enhance job prospects in this field.

How much does a Temporary ASIC Design Engineer make?

A Temporary ASIC Design Engineer typically earns between $40 and $70 per hour, depending on experience, location, and the complexity of the projects. Compensation may also include benefits such as flexible schedules and exposure to advanced design tools like Verilog and FPGA environments.

Is a temporary ASIC design engineer design difficult?

Designing as an ASIC design engineer can be complex due to the need for specialized knowledge in digital logic, hardware description languages, and verification tools. The difficulty varies based on project scope, experience, and familiarity with industry standards, but it generally requires strong technical skills and attention to detail.
Temporary Asic Design Engineer jobs near you
Infographic showing various Temporary Asic Design Engineer job openings in Williston, VT as of August 2026, with employment types broken down into 86% Full Time, 9% Part Time, and 5% Contract. Highlights an 86% Physical, 4% Hybrid, and 10% Remote job distribution, with an average salary of $154,912 per year, or $74.5 per hour.

Principal Technical Engineer 3rd Party IP Engineer

Marvell

Burlington, VT • On-site

Full-time

Life, Retirement

Posted 20 days ago

Job description

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

As a Principal Technical Engineer 3rd Party IP Engineer with Marvell, you'll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Storage, Security, and Networking. You'll be part of the 3rd party IP management team. In this role, you will work in parallel with a team of 3rd party IP engineers responsible for bringing in all subcontracted IP under the Marvell IP umbrella. This is a dynamic and challenging role, and, in this position, you will engage all parts of Marvell.

What You Can Expect

Looking for a talented 3rd party IP integration engineer to assist Marvell in offering DDR/LPDDR/GDDR/HBM/eMMC memory interface cores to our clients. Become part of a team creating leading-edge designs for the latest applications in artificial intelligence, hyper-scaler, communications, and storage. As a 3rd party core integrator, you will be involved in all stages of SoC development including defining core requirements, validating IP developer competence, overseeing core development, technology compliance, core integration, test compliance and silicon validation.

You will assist sales in winning bids by working with leading edge IP providers to meet customer requirements. You will manage 3rd party developers in completing core designs and providing required design rules. You will advise the Marvell design center on core integration into custom silicon designs and hold joint reviews with the design center and 3rd party IP provider. Post-silicon validation at customer sites will require a limited degree of travel. Responsibilities will also include developing statements of work, leading provider progress reviews, using 3rd party developer problem reporting tools to drive to problem resolution. You will assist with 8D follow-through for significant supplier issues.

What We're Looking For

  • Bachelor's degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience or Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience or equivalent professional experience in lieu of a formal degree

  • Proficient in understanding of DDR type interfaces (DDR, LPDDR, GDDR, HBM, eMMC), including the challenges associated with SoC PHY integration, timing analysis, packaging, and multi-chip integrated packaging

  • Proficient in project management tasks required to manage 3rd party developers

  • Broad-based exposure to ASIC design flows required for releasing a chip to fabrication including logic synthesis, physical design, timing, DRC/LVS, Formal verification and electrical checking

  • Good understanding of Design-For-Test concepts including DFT logic insertion, test generation, scan and embedded core testing

  • Good communication and customer management skills

Expected Base Pay Range (USD)

152,300 - 225,440, $ per annum

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life's most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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