ZipRecruiter

Log In

1

Tapeout Integration Engineer Jobs (NOW HIRING)

Meta

CAD and Integration Engineer, Silicon

Sunnyvale, CA · On-site

$212K - $294K/yr

... tapeout, and regression using Python, SKILL, and Tcl Minimum Qualifications • Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical ...

next page

Showing results 1-20

All JobsTechnology JobsSoftware JobsTapeout Integration Engineer Jobs

Tapeout Integration Engineer information

See salary details

$44.5K

$124.3K

$173.5K

How much do tapeout integration engineer jobs pay per year?

As of Sep 11, 2026, the average yearly pay for tapeout integration engineer in the United States is $124,275.00, according to ZipRecruiter salary data. Most workers in this role earn between $104,000.00 and $140,000.00 per year, depending on experience, location, and employer.

What is a tapeout integration engineer?

A Tapeout Integration Engineer is a professional who oversees the final stages of semiconductor chip design, ensuring that all design components are correctly integrated and ready for fabrication. They coordinate the various aspects of the design flow, including physical layout, verification, and documentation, to prepare the data for manufacturing. The role requires collaboration with design, verification, and manufacturing teams to address any last-minute issues and ensure the tapeout (final design submission) is successful. This position is critical for meeting production deadlines and achieving high-quality silicon results.

What are the key skills and qualifications needed to thrive as a tapeout integration engineer?

To thrive as a Tapeout Integration Engineer, you need a solid background in semiconductor device physics, VLSI design, and process integration, typically supported by a degree in electrical engineering or a related field. Proficiency with EDA tools such as Cadence, Synopsys, and scripting languages like Python or Perl, along with familiarity with tapeout flows, is crucial. Strong problem-solving skills, attention to detail, and effective communication are important soft skills for collaborating with cross-functional teams and managing complex projects. These skills ensure precise data handoff, minimize costly errors, and enable successful delivery of silicon products on schedule.

What are the typical challenges tapeout integration engineers face during the tapeout process and how are they managed?

Tapeout Integration Engineers often encounter challenges such as last-minute design changes, tight deadlines, and coordination among cross-functional teams like design, verification, and manufacturing. Managing these challenges requires strong project management skills, attention to detail, and effective communication to ensure all design specifications are met without errors. Proactive planning, regular status meetings, and maintaining clear documentation help mitigate risks and ensure a smooth handoff to fabrication. Collaboration with both internal and external stakeholders is crucial to address issues quickly and keep the project on schedule.

What is the difference between Tapeout Integration Engineer vs Chip Design Engineer?

AspectTapeout Integration EngineerChip Design Engineer
Required CredentialsBachelor's or Master's in Electrical Engineering, VLSI, or related fields; knowledge of EDA toolsBachelor's or Master's in Electrical Engineering, VLSI, or related fields; proficiency in hardware description languages
Work EnvironmentSemiconductor fabrication facilities, EDA tool environments, collaboration with design and manufacturing teamsDesign labs, CAD environments, collaboration with verification and manufacturing teams
Industry UsageUsed in semiconductor companies during tapeout phase to ensure design integrityUsed in chip design companies during the development phase to create functional hardware

The Tapeout Integration Engineer focuses on preparing and verifying integrated chip designs for manufacturing, ensuring design data is correctly finalized for tapeout. In contrast, the Chip Design Engineer primarily develops and simulates chip architectures and logic. Both roles require similar educational backgrounds and work in overlapping environments, but their core responsibilities differ in the design versus integration phases of chip development.

What are popular job titles related to Tapeout Integration Engineer jobs?

For Tapeout Integration Engineer jobs, the most frequently searched job titles are:

Infographic showing various Tapeout Integration Engineer job openings in the United States as of September 2026, with employment types broken down into 100% Full Time. Highlights an 100% In-person job distribution, with an average salary of $124,275 per year, or $59.7 per hour.

CAD and Integration Engineer, Silicon

Sunnyvale, CA

Meta
Internet and IT • 10K+ employees
Learn more about Metaexternal

$178K/yr

Full-time

Re-posted yesterday

Meta rating

7.8

Company rating: 7.8 out of 10

Based on 45 frontline employees who took The Breakroom Quiz

Job description

Meta is seeking a lead CAD and integration engineer to shape the methodology and physical implementation infrastructure for our custom silicon programs. Working at the intersection of circuit design, digital implementation, and physical verification, you will define and own the CAD flows that take designs from RTL and schematic intent through to foundry-ready GDS deliverables. You will establish best practices across synthesis, place-and-route, analog mixed-signal integration, and physical signoff, while building automation frameworks and integrating AI-assisted design tools to accelerate engineering velocity across the silicon team.
CAD and Integration Engineer, Silicon Responsibilities:
  • Define and own end-to-end digital implementation methodology including RTL-to-GDS flows, synthesis, place-and-route, DFT insertion, and multi-corner physical signoff
  • Lead analog mixed-signal physical integration strategy, establishing constraint authoring, floorplanning guidelines, and interface protocols between custom and digital domains
  • Develop and maintain CAD automation infrastructure using Python, SKILL, and Tcl to reduce manual effort across implementation, tapeout, and regression workflows
  • Integrate AI and LLM-assisted coding tools into CAD methodology to improve design automation productivity across the silicon engineering organization
  • Drive physical signoff convergence across timing, power, noise, and design rule checks to produce foundry-ready deliverables on schedule
  • Establish 3D integration and heterogeneous packaging flows including die-to-die interface planning, cross-die timing closure, and bump/interposer constraint management
  • Partner with foundry contacts on PDK qualification, design rule interpretation, and process design kit updates for leading-edge technology nodes
  • Define low-power implementation methodology including multi-voltage domain integration, UPF-based power intent authoring, and power analysis signoff
  • Provide technical direction to other engineers on CAD methodology decisions, flow architecture, and implementation best practices across multiple concurrent tapeout programs
  • Communicate implementation status, methodology decisions, and risk assessments to circuit designers, layout engineers, and program leadership

Minimum Qualifications:
  • 8+ years of industry experience in VLSI CAD, physical implementation, or silicon design methodology across multiple technology nodes and tapeouts
  • Expertise in full RTL-to-GDS digital implementation flows including synthesis, place-and-route, DFT, and multi-corner physical signoff using industry-standard EDA tools
  • Experience with analog mixed-signal physical integration including constraint authoring, floorplan coordination, and interface management between custom and digital design domains
  • Proficiency in scripting and automation using Python, SKILL, Tcl, or equivalent languages to build and maintain CAD flow infrastructure
  • Experience communicating methodology decisions, tapeout risk, and implementation status to cross-functional partners including circuit designers, layout engineers, and foundry contacts

Preferred Qualifications:
  • Experience with 3D stacking or advanced packaging flows including die-to-die interface planning, cross-die timing analysis, and heterogeneous integration methodology
  • Experience with PDK qualification and design rule development in direct collaboration with foundry partners on leading-edge process nodes
  • Background in low-power design methodology including UPF-based power intent, multi-voltage domain integration, and power signoff for mobile or wearable silicon applications
  • Familiarity with AI-assisted design tools or LLM-based coding assistants applied to CAD automation or implementation flow development

About Meta:
Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.
Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.
Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@meta.com.
$178,000/year to $250,000/year + bonus + equity + benefits
Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.

What Meta employees say

Pay

Benefits

Hours and flexibility

Workplace

Get the full story on Breakroom

Apply