... integrated engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC ... Description Develop microarchitecture and RTL for a System-on-Chip (SoC) IP design, aligning with ...
... integrated engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC ... Description Develop microarchitecture and RTL for a System-on-Chip (SoC) IP design, aligning with ...
SoC Design Engineer
$110K - $140K/yr
Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
SoC Design Engineer
$110K - $140K/yr
Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
... energy-efficient design and new technologies that transform the user experience at the product ... As a member of the team, you will work closely with SoC architects and IP developers to develop ...
... energy-efficient design and new technologies that transform the user experience at the product ... As a member of the team, you will work closely with SoC architects and IP developers to develop ...
... energy-efficient design and new technologies that transform the user experience at the product ... As a member of the team, you will work closely with SoC architects and IP developers to develop ...
... energy-efficient design and new technologies that transform the user experience at the product ... As a member of the team, you will work closely with SoC architects and IP developers to develop ...
SoC Design Engineer
$110K - $140K/yr
Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
SoC Design Engineer
$110K - $140K/yr
Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
SoC Design Engineer
$110K - $140K/yr
Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
SoC Design Engineer
$110K - $140K/yr
Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
SoC Design Engineer
Santa Clara, CA · On-site
$110K - $140K/yr
Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
SoC Design Engineer
Santa Clara, CA · On-site
$110K - $140K/yr
Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
RTL Design Engineer - Wireless SoC
San Jose, CA · Remote
$55 - $60/hr
RTL Design Engineer - Wireless SoC Location: Remote Job Type: Contract We are seeking an experienced RTL Design Engineer to work on next-generation wireless SoC development. The ideal candidate will ...
Quick apply
RTL Design Engineer - Wireless SoC
San Jose, CA · Remote
$55 - $60/hr
RTL Design Engineer - Wireless SoC Location: Remote Job Type: Contract We are seeking an experienced RTL Design Engineer to work on next-generation wireless SoC development. The ideal candidate will ...
SoC Design Engineer
Santa Clara, CA · On-site
Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
Quick apply
SoC Design Engineer
Santa Clara, CA · On-site
Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
SoC Design Engineer
Santa Clara, CA · On-site
Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
Quick apply
SoC Design Engineer
Santa Clara, CA · On-site
Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
Debug SoC Design Engineer
Irvine, CA · On-site
$146K - $178K/yr
You will work closely with SoC architects and IP developers to define debug features that meet the power, performance, and area goals. You will own the design for the debug and trace hub. You will ...
Debug SoC Design Engineer
Irvine, CA · On-site
$146K - $178K/yr
You will work closely with SoC architects and IP developers to define debug features that meet the power, performance, and area goals. You will own the design for the debug and trace hub. You will ...
Debug SoC Design Engineer
Irvine, CA · On-site
$146K - $178K/yr
You will work closely with SoC architects and IP developers to define debug features that meet the power, performance, and area goals. You will own the design for the debug and trace hub. You will ...
Debug SoC Design Engineer
Irvine, CA · On-site
$146K - $178K/yr
You will work closely with SoC architects and IP developers to define debug features that meet the power, performance, and area goals. You will own the design for the debug and trace hub. You will ...
... integrated engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC ... Description Develop microarchitecture and RTL for a System-on-Chip (SoC) IP design, aligning with ...
... integrated engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC ... Description Develop microarchitecture and RTL for a System-on-Chip (SoC) IP design, aligning with ...
SoC Design Engineer
$110K - $140K/yr
Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
SoC Design Engineer
$110K - $140K/yr
Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
Debug SoC Design Engineer
$122K - $214K/yr
You will work closely with SoC architects and IP developers to define debug features that meet the power, performance, and area goals. You will own the design for the debug and trace hub. You will ...
Debug SoC Design Engineer
$122K - $214K/yr
You will work closely with SoC architects and IP developers to define debug features that meet the power, performance, and area goals. You will own the design for the debug and trace hub. You will ...
SoC Design Engineer
Santa Clara, CA · On-site
$110K - $140K/yr
Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
SoC Design Engineer
Santa Clara, CA · On-site
$110K - $140K/yr
Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
SoC Design Engineer
Santa Clara, CA · On-site
$110K - $140K/yr
Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
SoC Design Engineer
Santa Clara, CA · On-site
$110K - $140K/yr
Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
SoC Design Engineer
$110K - $140K/yr
Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
SoC Design Engineer
$110K - $140K/yr
Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
SoC Design Engineer
Santa Clara, CA · On-site
$110K - $140K/yr
Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
SoC Design Engineer
Santa Clara, CA · On-site
$110K - $140K/yr
Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
SoC Design Engineer
$110K - $140K/yr
Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
SoC Design Engineer
$110K - $140K/yr
Knowledge of high performance and low power design techniques. * Knowledge of FPGA and emulation platforms. * Knowledge of SOC architecture. * Knowledge of assertion-based formal verification is a ...
Summer Soc Design Engineer information
See salary details
$40.5K - $51.2K
2% of jobs
$51.2K - $62K
11% of jobs
$67.7K is the 25th percentile. Wages below this are outliers.
$62K - $72.7K
23% of jobs
The median wage is $79.6K / yr.
$72.7K - $83.4K
22% of jobs
$83.4K - $94.1K
17% of jobs
$94.4K is the 75th percentile. Wages above this are outliers.
$94.1K - $104.9K
9% of jobs
$104.9K - $115.6K
6% of jobs
$115.6K - $126.3K
3% of jobs
$126.3K - $137K
3% of jobs
$137K - $147.8K
2% of jobs
$147.8K - $158.5K
1% of jobs
$40.5K
$88.2K
$158.5K
How much do summer soc design engineer jobs pay per year?
As of Jul 17, 2026, the average yearly pay for summer soc design engineer in the United States is $88,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $68,000.00 and $98,500.00 per year, depending on experience, location, and employer.
What cities are hiring for Summer Soc Design Engineer jobs? Cities with the most Summer Soc Design Engineer job openings:
What are the most commonly searched types of Soc Design Engineer jobs? The most popular types of Soc Design Engineer jobs are:
What states have the most Summer Soc Design Engineer jobs? States with the most job openings for Summer Soc Design Engineer jobs include:
Apple rating
8.1
Based on 670 frontline employees who took The Breakroom Quiz
5th of 30 rated technology retailers
Job description
Come join Apple's growing wireless silicon development team. Our wireless SOC organization is responsible for all aspects of wireless silicon development. With a particular emphasis on highly energy-efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. If you enjoy a fast-paced and challenging environment and collaborating with people across different functional areas as well as thriving during crisis times, we encourage you to apply.
Description
Develop microarchitecture and RTL for a System-on-Chip (SoC) IP design, aligning with specified functional requirements. Engage in hardware/software partitioning discussions with software and firmware teams. Collaborate cross-functionally to ensure successful SoC integration, supporting design verification and validation across all phases-from concept to silicon bring-up. Work closely with physical design, DFT, and CAD teams to optimize performance, power, and area (PPA) targets while ensuring design quality and maintainability.
Minimum Qualifications
BS and 10+ years of relevant industry experience.
Skilled in defining ASIC microarchitecture to meet functional requirements while managing performance, power, and area trade-offs.
Knowledgeable about the ASIC design flow, including System Verilog RTL implementation, Lint, CDC, RDC, Synthesis and STA.
Preferred Qualifications
Expertise in design domains such as memory subsystems, bus interfaces, CPU integration, DMA engines, Compression, Security IP design, and high-speed/low-speed peripherals like PCIE, QSPI, UART, and SPMI.
Thorough understanding of cross clock-domain design principles and associated CDC requirements.
Familiarity with ASIC low power design techniques, including multiple supply domains configuration, dynamic power/clock scaling, and power analysis.
Familiarity with ASIC test methodologies, encompassing DFT, scan insertion, memory BIST, and other related techniques.
Strong communication skills, both written and oral.
Description
Develop microarchitecture and RTL for a System-on-Chip (SoC) IP design, aligning with specified functional requirements. Engage in hardware/software partitioning discussions with software and firmware teams. Collaborate cross-functionally to ensure successful SoC integration, supporting design verification and validation across all phases-from concept to silicon bring-up. Work closely with physical design, DFT, and CAD teams to optimize performance, power, and area (PPA) targets while ensuring design quality and maintainability.
Minimum Qualifications
BS and 10+ years of relevant industry experience.
Skilled in defining ASIC microarchitecture to meet functional requirements while managing performance, power, and area trade-offs.
Knowledgeable about the ASIC design flow, including System Verilog RTL implementation, Lint, CDC, RDC, Synthesis and STA.
Preferred Qualifications
Expertise in design domains such as memory subsystems, bus interfaces, CPU integration, DMA engines, Compression, Security IP design, and high-speed/low-speed peripherals like PCIE, QSPI, UART, and SPMI.
Thorough understanding of cross clock-domain design principles and associated CDC requirements.
Familiarity with ASIC low power design techniques, including multiple supply domains configuration, dynamic power/clock scaling, and power analysis.
Familiarity with ASIC test methodologies, encompassing DFT, scan insertion, memory BIST, and other related techniques.
Strong communication skills, both written and oral.
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976