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Sta Static Timing Analysis Engineer Jobs in Indiana

The PAC Group

Material Packaging Engineer

Warsaw, IN

... timing. Qualifications * Bachelor's degree in Packaging Engineering, Industrial Engineering ... Strong analytical, problem-solving, communication, and project management skills. * Able to work ...

The PAC Group

Material Packaging Engineer

Warsaw, IN · On-site

$70/hr

... timing. Qualifications * Bachelor's degree in Packaging Engineering, Industrial Engineering ... Strong analytical, problem-solving, communication, and project management skills. * Able to work ...

Braunability

Engineer II

Winamac, IN

TheMechanical EngineerIIto driveour VA/VE (Value Analysis / Value Engineering) initiatives.He ... Constantly improve designs,processes,and timing,maintainingproject specifications. Participate ...

Braunability

Engineer II

Winamac, IN

Track system cost, timing, and technical risks while leading mitigation activities. Release ... Ability to communicate simulation needs and perform analysis where possible. Proficient in ...

Saab Automobile AB

Lead Stress Engineer

West Lafayette, IN · On-site

$115K - $150K/yr

The Lead Stress/MRB Engineer will work in both an MRB/Liaison and stress engineering capacity. In ... Perform static and DaDT structural analyses of metallic and/or composite airframe structure ...

BraunAbility

Engineer II

Winamac, IN · On-site

The Mechanical Engineer II to drive our VA/VE (Value Analysis / Value Engineering) initiatives. He ... Constantly improve designs, processes, and timing, maintaining project specifications. Participate ...

BraunAbility

Engineer II

Winamac, IN · On-site

Track system cost, timing, and technical risks while leading mitigation activities. Release ... Ability to communicate simulation needs and perform analysis where possible. Proficient in ...

SAIC

Senior Mach-TB Mission Engineer

Crane, IN

$104K - $143K/yr

This individual will help lead pre- and post-mission analysis activities, overseeing on-site ... timing signals from the Range or Vehicle provider. * Process telemetry inputs to generate the ...

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Sta Static Timing Analysis Engineer information

What is a STA static timing analysis engineer?

STA (Static Timing Analysis) Engineers are specialists in the semiconductor industry who analyze and verify the timing performance of digital circuits without requiring dynamic simulation. They use specialized software tools to ensure that signal transitions occur within required time constraints, preventing issues like data corruption or circuit malfunction. Their work is crucial in the design and validation stages of integrated circuits (ICs), helping to guarantee that chips will function reliably at specified speeds and under different conditions.

What are some common challenges faced by STA static timing analysis engineers during project cycles?

STA Static Timing Analysis Engineers often encounter challenges related to tight project deadlines and complex design specifications. Balancing multiple design corners, managing timing closure for increasingly smaller technology nodes, and coordinating with physical design, synthesis, and verification teams are key hurdles. Additionally, staying updated with evolving EDA tools and methodologies is essential to ensure accurate analysis. Effective communication and troubleshooting skills are critical to resolve timing violations and deliver high-quality silicon on schedule.

What are the key skills and qualifications needed to thrive as a STA static timing analysis engineer?

To thrive as a Static Timing Analysis Engineer, you need a solid background in digital circuit design, timing concepts, and typically a degree in electrical or computer engineering. Proficiency with EDA tools such as Synopsys PrimeTime, Cadence Tempus, and scripting languages like TCL or Perl is essential. Strong problem-solving abilities, attention to detail, and effective communication skills set top performers apart in this role. These competencies ensure accurate timing verification, efficient collaboration, and successful delivery of complex semiconductor projects.
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Infographic showing various Sta Static Timing Analysis Engineer job openings in Indiana as of June 2026, with employment types broken down into 68% Full Time, 3% Part Time, 28% Contract, and 1% Nights. Highlights an 84% Physical, 3% Hybrid, and 13% Remote job distribution.

Senior Signal Processor (SIGPRO) Engineer SPY-1

Kratos Defense

Crane, IN

Full-time

Re-posted 9 days ago

Kratos Defense & Security Solutions rating

7.8

Company rating: 7.8 out of 10

Based on 10 frontline employees who took The Breakroom Quiz

Job description

Kratos is seeking an experienced Senior Signal Processor (SIGPRO) Engineer to support the sustainment, overhaul, and modernization of the AN/SPY-1 radar system, with a specific focus on the signal processor subsystem. The SME will provide in-depth technical guidance across engineering, sustainment, and depot-level repair planning. This position plays a critical role in restoring and modernizing radar capabilities by supporting design recovery, system troubleshooting, test strategy development, and obsolescence resolution for legacy digital and analog processing architectures.

Key Responsibilities:

  • Serve as the technical lead for the AN/SPY-1 Signal Processor subsystem across all radar variants (D, D(V), D(MOD)).
  • Lead efforts to analyze and document the design and functional behavior of legacy signal processor components, including digital processing modules, interface cards, and timing assemblies.
  • Support design recovery and traceability efforts, working from GFI, limited technical data, or harvested hardware.
  • Define and support the development of prototype subassemblies, repair processes, and test capabilities to validate organic sustainment approaches.
  • Develop and validate functional test procedures, signal flow diagrams, and performance benchmarks.
  • Identify critical components at risk due to obsolescence, and support alternate part qualification, reverse engineering, or redesign as necessary.
  • Coordinate with systems engineers, test engineers, and OEM partners to ensure alignment with weapon system interface requirements and mission-critical timing/data processing functionality.
  • Provide technical input to Integrated Technical Data Packages (ITDPs), depot stand-up planning, and operator/maintainer training materials.
  • Ensure test and repair processes comply with NAVSEA and METCAL standards where applicable.

Required Qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.
  • Minimum of 10+ years of experience with radar or advanced signal processing systems, including 5+ years supporting AN/SPY-1 or equivalent phased array radar systems.
  • Deep understanding of legacy digital processing architectures, A/D conversion, timing synchronization, and signal conditioning.
  • Experience with diagnostics, troubleshooting, and repair at the board and component level.
  • Familiarity with tools used for signal integrity analysis, logic analyzers, and boundary scan testing.
  • Proven ability to read, interpret, and reverse-engineer technical data, schematics, and embedded processing logic.
  • Experience developing or reviewing test procedures and technical documentation for government sustainment programs.
  • Active Secret Clearance
 

Preferred Qualifications:

  • Prior work with AEGIS Combat System interfaces, SPY-1 timing architectures, or radar track processing functions.
  • Familiarity with DoD obsolescence mitigation strategies, including reverse engineering, emulation, and form-fit-function redesign.
  • Experience supporting ORDALT implementation, depot activation, or prototype validation.
  • Knowledge of Model-Based Systems Engineering (MBSE) practices or digital engineering toolsets.
  • Active TS/SCI Clearance
 

Travel: ~10-20%, including to shipyards, government labs, and partner facilities.

(No phone calls please)

 #LI-AC1

#LI-Onsite

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