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Sta Static Timing Analysis Engineer Jobs in Indiana

Stress Analyst

Indianapolis, IN · On-site

$60 - $64/hr

The role will focus on structural analysis of static components such as casings, bearing supports ... Bachelor's degree in Engineering or Physics with 2+ years of experience, or a Master's, or a PhD in ...

New

Project

Fishers, IN · On-site

$89K - $116K/yr

Cascade project timing down to Purchasing, STA, Suppliers, Plants, Process Engineering, and other ... Analysis (FEA), Failure Mode and Effects Analysis (FMEA), and engineering problem-solving ...

Engineering and Sciences Subcategory: Electrical Engr Schedule: Full-Time Shift: Day Job Travel ... Monitor and analyze real‑time model execution timelines * Resolve timing issues affecting ...

Monitor and analyze real-time model execution timelines * Resolve timing issues affecting weapon ... Collaborate closely with system engineers, software developers, real-time modelers, and test ...

Engineering and Sciences Subcategory: Electrical Engr Schedule: Full-Time Shift: Day Job Travel ... Monitor and analyze real-time model execution timelines * Resolve timing issues affecting weapon ...

Cascade project timing down to Purchasing, STA, Suppliers, Plants, Process Engineering, and other ... Analysis (FEA), Failure Mode and Effects Analysis (FMEA), and engineering problem-solving ...

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Sta Static Timing Analysis Engineer information

What is a STA static timing analysis engineer?

STA (Static Timing Analysis) Engineers are specialists in the semiconductor industry who analyze and verify the timing performance of digital circuits without requiring dynamic simulation. They use specialized software tools to ensure that signal transitions occur within required time constraints, preventing issues like data corruption or circuit malfunction. Their work is crucial in the design and validation stages of integrated circuits (ICs), helping to guarantee that chips will function reliably at specified speeds and under different conditions.

What are some common challenges faced by STA static timing analysis engineers during project cycles?

STA Static Timing Analysis Engineers often encounter challenges related to tight project deadlines and complex design specifications. Balancing multiple design corners, managing timing closure for increasingly smaller technology nodes, and coordinating with physical design, synthesis, and verification teams are key hurdles. Additionally, staying updated with evolving EDA tools and methodologies is essential to ensure accurate analysis. Effective communication and troubleshooting skills are critical to resolve timing violations and deliver high-quality silicon on schedule.

What are the key skills and qualifications needed to thrive as a STA static timing analysis engineer?

To thrive as a Static Timing Analysis Engineer, you need a solid background in digital circuit design, timing concepts, and typically a degree in electrical or computer engineering. Proficiency with EDA tools such as Synopsys PrimeTime, Cadence Tempus, and scripting languages like TCL or Perl is essential. Strong problem-solving abilities, attention to detail, and effective communication skills set top performers apart in this role. These competencies ensure accurate timing verification, efficient collaboration, and successful delivery of complex semiconductor projects.
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Infographic showing various Sta Static Timing Analysis Engineer job openings in Indiana as of June 2026, with employment types broken down into 68% Full Time, 3% Part Time, 28% Contract, and 1% Nights. Highlights an 84% Physical, 3% Hybrid, and 13% Remote job distribution.

Sr Principal Electrical Engineer - ASIC/FPGA (Onsite)

Prattwhitney

Fort Wayne, IN • On-site

$150 - $200/hr

Other

Medical, Dental, Vision, Life, Retirement, PTO

Posted 2 days ago

New


Job description

Senior Principal Electrical or Computer Engineer – Microelectronics Technology

Collins Aerospace, a division of RTX, is seeking an experienced Senior Principal Electrical or Computer Engineer to support the design, development, and integration of advanced digital ASIC and FPGA solutions for next‑generation aerospace and defense applications. This onsite role will be based out of Fort Wayne, IN and requires the ability to obtain and maintain a U.S. government issued security clearance (DoD Secret).

Responsibilities
  • Capture requirements and design digital ASIC/FPGA architecture, including RTL development, timing analysis, closure, verification, and system integration.
  • Identify and implement tools, methodologies, and best practices to continuously improve the ASIC/FPGA design flow.
  • Contribute to engineering estimates and technical planning for new program pursuits.
  • Plan and execute project‑level work while ensuring alignment to schedule, cost, and performance objectives.
  • Provide technical leadership for design teams by defining scope, coordinating activities, and reporting status.
  • Facilitate cross‑functional collaboration throughout the development lifecycle to ensure successful delivery of high‑performance digital solutions.
QualificationsRequired
  • Degree in Science, Technology, Engineering or Mathematics (STEM) or equivalent experience; minimum 10 years of relevant experience, or advanced degree with minimum 7 years of experience.
  • U.S. citizenship and ability to obtain a valid DoD Secret security clearance.
  • Hands‑on experience with RTL design, coding, and simulation using VHDL and/or Verilog.
  • At least 5 years’ experience in digital circuit architecture, resource optimization, timing analysis, and timing closure.
  • At least 5 years’ experience developing and executing RTL verification testbenches using VHDL or SystemVerilog.
  • Proficiency with ASIC and/or FPGA simulation, synthesis, and implementation tools (ModelSim, Synplify, Quartus, Vivado, or similar).
  • Proven ability to lead cross‑functional engineering teams while managing project scope, schedules, budgets, and technical deliverables.
Preferred
  • Experience with ASIC/FPGA lab validation and debugging using standard lab equipment; familiarity with DFT, manufacturability, and production test concepts.
  • Proficiency with Unix/Linux environments and scripting or software development (C, C++, Python, Perl, or shell).
  • Industry‑standard ASIC/FPGA simulation and synthesis tools such as QuestaSim, Synplify, Quartus, or Vivado.
  • Strong written and verbal communication skills, with the ability to work independently and collaboratively in fast‑paced, multidisciplinary engineering environments.
Benefits
  • Medical, dental, and vision insurance
  • Three weeks of vacation for newly hired employees
  • Generous 401(k) plan with employer matching funds and separate retirement contribution including a Lifetime Income Strategy option
  • Tuition reimbursement program
  • Student loan repayment program
  • Life insurance and disability coverage with optional additional coverages (pet, home, auto insurance, and critical illness insurance)
  • Birth, adoption, parental leave benefits
  • Health and wellness programs (virtual doctor visits, wellness rewards, etc.)
  • Relocation assistance availability
Equal Opportunity Employer

RTX is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability, or veteran status. RTX provides affirmative action in employment for qualified individuals with a disability and protected veterans in compliance with applicable laws.

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