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Soc Design Verification Manager Jobs (NOW HIRING)

Wireless SOC Verification Engineer

Irvine, CA · On-site

$146K - $178K/yr

As part of the Wireless SOC team, you will have the opportunity to verify complex SOCs. Our team ... As a Design Verification Engineer on our team, you'll be at the center of the verification effort ...

As a Design Verification Engineer on our team, you'll be at the center of the verification effort ... Deliver on Power Management designs using low-power methodologies and power up-down scenarios using ...

As a Design Verification Engineer on our team, you'll be at the center of the verification effort ... Deliver on Power Management designs using low-power methodologies and power up-down scenarios using ...

As a Design Verification Engineer on our team, you'll be at the center of the verification effort ... Deliver on Power Management designs using low-power methodologies and power up-down scenarios using ...

As a Design Verification Engineer on our team, you'll be at the center of the verification effort ... Deliver on Power Management designs using low-power methodologies and power up-down scenarios using ...

As a Design Verification Engineer on our team, you'll be at the center of the verification effort ... Deliver on Power Management designs using low‑power methodologies and power up‑down scenarios ...

... SOC Design Verification, Emulation, Formal verification, STA, and Physical Design teams ... management designs desirable. Ability to communicate effectively across all internal groups.

... SOC Design Verification, Emulation, Formal verification, STA, and Physical Design teams ... management designs desirable. Ability to communicate effectively across all internal groups.

Silicon Design Verification Manager

Austin, TX · On-site

$134K - $164K/yr

Object Oriented design verification coding (System Verilog or C++); Testbench architecture design using agents, stimulus, checkers, and scoreboards; and Simulation-based verification at block and ...

Senior ASIC/SoC Design Verification Engineer (Chip-Level Verification) An outstanding, full-time opening is available in Silicon Valley, CA for an experienced ASIC/SoC Design Verification Engineer ...

SoC Design Engineer

Santa Clara, CA · On-site

$156K - $160K/yr

SoC Design Engineer Job Duties: Be responsible for digital design of ASIC cores within image sensor ... Conduct design verification and modeling using SVA, Python, Perl, C++/C, and HLS. Work with digital ...

Showing results 41-60

Soc Design Verification Manager information

See salary details

$42K

$114.5K

$201.5K

How much do soc design verification manager jobs pay per year?

As of Sep 13, 2026, the average yearly pay for soc design verification manager in the United States is $114,491.00, according to ZipRecruiter salary data. Most workers in this role earn between $83,500.00 and $144,000.00 per year, depending on experience, location, and employer.

What does a SoC Design Verification Manager do?

A SoC (System on Chip) Design Verification Manager oversees the verification process for complex integrated circuits, ensuring that the chip design functions as intended before manufacturing. This role involves leading a team of engineers, defining verification strategies, managing schedules, and coordinating with design and architecture teams. The manager is responsible for planning and executing verification methodologies such as simulation, emulation, and formal verification. They also ensure that all design requirements and quality standards are met, and play a key role in risk management and problem resolution throughout the verification lifecycle.

What are the key skills and qualifications needed to thrive as a SoC Design Verification Manager?

To thrive as a SoC Design Verification Manager, you need deep expertise in digital design, verification methodologies (such as UVM or SystemVerilog), and a relevant engineering degree. Proficiency with industry-standard EDA tools (like Synopsys, Cadence, or Mentor Graphics), scripting languages, and often project management certifications is vital. Strong leadership, communication, and problem-solving skills help you manage teams and coordinate across multiple disciplines. These capabilities are crucial for ensuring high-quality, timely delivery of complex SoC projects in a competitive semiconductor environment.

What are some common challenges faced by a SoC Design Verification Manager when leading verification teams?

As an SoC Design Verification Manager, you may encounter challenges such as coordinating verification efforts across multiple IP blocks, managing shifting project timelines, and ensuring thorough test coverage within tight deadlines. Balancing resource allocation while adapting to evolving design specifications is common, requiring strong communication and organizational skills. Additionally, fostering collaboration between verification engineers, design teams, and software teams is crucial to identify and resolve issues early, ensuring high-quality silicon delivery.

What is the difference between Soc Design Verification Manager vs Soc Design Engineer?

AspectSoc Design Verification ManagerSoc Design Engineer
Primary FocusOversees verification processes, manages teams, ensures verification coverageDesigns and develops SoC components, implements verification tests
Required SkillsVerification methodologies, team leadership, project managementHardware description languages, verification tools, circuit design
Work EnvironmentManagement, coordination, high-level planningHands-on design, coding, testing
CertificationsOften requires verification-related certifications, relevant degreesEngineering degrees, hardware verification certifications

The Soc Design Verification Manager primarily oversees verification teams and processes, focusing on project management and verification coverage. In contrast, the Soc Design Engineer is involved in the hands-on design and implementation of SoC components. Both roles require strong technical skills and relevant certifications, but their responsibilities differ in scope and focus.

What are popular job titles related to Soc Design Verification Manager jobs?

For Soc Design Verification Manager jobs, the most frequently searched job titles are:

Infographic showing various Soc Design Verification Manager job openings in the United States as of September 2026, with employment types broken down into 100% Full Time. Highlights an 100% In-person job distribution, with an average salary of $114,491 per year, or $55 per hour.

Wireless SOC Verification Engineer

Irvine, CA • On-site

Apple
Computer and Electronic Product Manufacturing • 10K+ employees

$146K - $178K/yr

Full-time

Re-posted 8 days ago


Apple rating

8.1

Company rating: 8.1 out of 10

Based on 684 frontline employees who took The Breakroom Quiz


Job description

"Be the change you want to see in the world." The brand new, Apple designed Wireless/Bluetooth chips are at the heart of Networking in the newest iPhones. As part of the Wireless SOC team, you will have the opportunity to verify complex SOCs. Our team integrates multiple sophisticated IP level DV environments, craft highly reusable best-in-class UVM Testbenches, implement effective coverage driven and directed test cases, deploy new AI tools, and implement methodologies to improve quality of tape-out readiness. By collaborating with other product development groups across Apple, you can push the industry boundaries of what wireless systems can do and improve the product experience for our customers across the world!
Description
You will learn all aspects of a large-scale SOC, different types of SOC architectures, high speed layered protocols, low-power driven architecture, and best-in-class DV methodology. You will gain knowledge on Wireless protocols, FW-HW interactions, and complexities of multi-chip SOC debug architecture. As a Design Verification Engineer on our team, you'll be at the center of the verification effort within our silicon design group responsible for crafting and productizing state of the art Wireless SOCs. This position comes with responsibility for pre-silicon RTL verification of block and top-level SOC, all aspects of SOC Design Verification engineering, and will enable you to thrive in a dynamic multi-functional organization, debate ideas openly, and deliver on complex Wireless protocol chip requirements.
Minimum Qualifications
BS and a minimum of 10 years relevant industry experience.
Proven track record of working full ASIC cycle from concept to tape-out to bring-up, including test-planning, testbench implementation, test sequence creation and debugging, and coverage closure.
Expertise in SystemVerilog coding and UVM methodology
Preferred Qualifications
Dedicated/hands-on ASIC & SOC DV experience.
Experience taping out large SOC systems with embedded processor cores.
Hands-on verification experience of PCIe, Bus Fabric, NOC, AHB, AXI, based bus architecture in UVM environment.
Experience with Formal Verification.
In-depth knowledge and experience working with low power design, UPF integration, boot-up, power-cycling, HW/FW interaction verification.
Low Power Verification experience.
Should be a great teammate with excellent communication and problem-solving skills and the desire to seek diverse challenges.

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About Apple

Sourced by ZipRecruiter

Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.

Industry

Computer and electronic product manufacturing

Company size

10,000+ Employees

Headquarters location

Cupertino, CA, US

Year founded

1976