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Soc Design Verification Manager Director Jobs (NOW HIRING)

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Design Verification Manager

Sunnyvale, CA · On-site

$161K - $197K/yr

Design Verification Manager Who We Are: Hewlett Packard Enterprise is the global edge-to-cloud ... Define global verification strategies, infrastructure, and execution plans for complex SoC and IP ...

Qualcomm

SOC Design Verification Engineer

San Diego, CA · On-site

$144K - $176K/yr

Create directed and constrained-random test scenarios to validate functionality and architectural ... Security, RAS, and power-management features * Support emulation and acceleration-based ...

Qualcomm

SOC Design Verification Engineer

San Diego, CA · On-site

$98K - $147K/yr

... design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC ... Level of Responsibility: • Works under supervision. • Decision-making affects direct area of ...

Qualcomm

SOC Design Verification Engineer

San Diego, CA · On-site

$98K - $147K/yr

... design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC ... Decision-making affects direct area of work and/or work group. * Requires verbal and written ...

Qualcomm

SOC Design Verification Engineer

San Diego, CA · On-site

$98K - $147K/yr

... design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC ... Level of Responsibility: • Works under supervision. • Decision-making affects direct area of ...

Apple

Wireless SOC Verification Engineer

Irvine, CA · On-site

$122K - $214K/yr

... directed test cases, deploy new AI tools, and implement methodologies to improve quality of tape ... As a Design Verification Engineer on our team, you'll be at the center of the verification effort ...

Apple

Wireless SOC Verification Engineer

Irvine, CA · On-site

$146K - $178K/yr

... directed test cases, deploy new AI tools, and implement methodologies to improve quality of tape ... As a Design Verification Engineer on our team, you'll be at the center of the verification effort ...

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Soc Design Verification Manager Director information

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How much do soc design verification manager director jobs pay per year?

As of Sep 13, 2026, the average yearly pay for soc design verification manager director in the United States is $135,763.00, according to ZipRecruiter salary data. Most workers in this role earn between $109,500.00 and $163,000.00 per year, depending on experience, location, and employer.

What does a SoC Design Verification Manager Director do?

A SoC (System on Chip) Design Verification Manager Director oversees teams responsible for ensuring that complex integrated circuits function as intended before manufacturing. They lead the development and execution of verification strategies, manage schedules and resources, and collaborate closely with design, architecture, and validation teams. Their role is critical in identifying and resolving design flaws early in the product development process, thereby improving quality and reducing costly errors. Additionally, they mentor verification engineers and help shape verification methodologies to keep pace with evolving technology.

What are some common challenges faced by a SoC Design Verification Manager Director, and how can they be addressed?

One of the most common challenges for an SoC Design Verification Manager Director is balancing the need for thorough verification coverage with tight project deadlines. Coordinating large, cross-functional teams and integrating verification activities across multiple IP blocks adds complexity. Effective communication, robust planning, and leveraging automation tools can help streamline processes and ensure high-quality outcomes. Encouraging a culture of continuous improvement and fostering collaboration between design and verification teams are also key to overcoming these challenges.

What are the key skills and qualifications needed to thrive as a SoC Design Verification Manager Director, and why are they important?

To thrive as a SoC Design Verification Manager Director, you need deep expertise in digital design, verification methodologies (such as UVM or SystemVerilog), and a strong background in electrical or computer engineering, often with an advanced degree. Familiarity with industry-standard EDA tools (like Cadence, Synopsys, or Mentor Graphics) and experience leading verification teams are typically required. Outstanding leadership, strategic planning, and communication skills help in coordinating large teams and cross-functional projects. These capabilities are crucial for delivering complex SoC products on schedule and ensuring their reliability and performance in competitive markets.

What are popular job titles related to Soc Design Verification Manager Director jobs?

For Soc Design Verification Manager Director jobs, the most frequently searched job titles are:

SoC Design Verification Engineer

San Jose, CA • On-site

E-Solutions, Inc.
See more jobs at E-Solutions, Inc.external

$159K - $194K/yr

Other

Posted 23 days ago

Job description

Position Title: SoC Design Verification Engineer

Location: San Jose, CA

Remote/Onsite: Onsite

Types of Hire: Fulltime

Job Description: -

We are looking for a highly skilled SoC/Performance DV engineer to drive system-level validation and performance characterization of complex SoCs. The role involves working closely with architecture, design, and software teams to ensure silicon meets performance, power, and functionality targets.

 

Key Responsibilities:

 

  • Develop and execute SoC-level validation and performance verification strategy
  • Build system-level testbenches, workloads, and performance models
  • Analyze performance bottlenecks across CPU, memory, interconnect, and accelerators
  • Perform power and performance trade-off analysis
  • Collaborate with architecture, RTL, and software teams
  • Debug issues at system level (HW + FW/SW interaction)

 

Required Skills:

              Strong experience in SoC-level DV / Performance validation

  • Understanding of CPU architecture, memory hierarchy, NoC/interconnect
  • Expertise in SystemVerilog/UVM + C/C++/Python
  • Experience with performance profiling tools
  • Strong debugging and analytical skills

 Good to Have:

 

Experience in post-silicon validation / bring-up

Knowledge of AI/ML or high-performance computing workloads

Disclaimer: E-Solutions Inc. provides equal employment opportunities (EEO) to all employees and applicants for employment without regard  to race, color, religion, gender, sexual orientation, gender identity or expression, national origin, age, disability, genetic information, marital status, amnesty, or status as a covered veteran in accordance with applicable federal, state and local laws. We especially invite women, minorities, veterans, and individuals with disabilities to apply. EEO/AA/M/F/Vet/Disability.”


SoC Design Verification Engineer1Python,UVM,Verilog,SOC,Design Verification,CPUN/AFull TImeUnited States

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