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Soc Design Verification Manager Director Jobs (NOW HIRING)

Custom Circuits Design Verification Engineer

Austin, TX ยท On-site

$134K - $164K/yr

Design Verification Engineers at Apple are responsible for verifying the functionality and ... In this highly visible role, you will be at the center of a SoC design effort collaborating with ...

Custom Circuits Design Verification Engineer

Austin, TX ยท On-site

$134K - $164K/yr

Design Verification Engineers at Apple are responsible for verifying the functionality and ... In this highly visible role, you will be at the center of a SoC design effort collaborating with ...

SoC Design Engineer Job Duties: Be responsible for digital design of ASIC cores within image sensor ... Conduct design verification and modeling using SVA, Python, Perl, C++/C, and HLS. Work with digital ...

... SOC Design Verification, Emulation, STA, and Physical Design teams - Collaborate with software and systems teams to ensure a high quality product Minimum Qualifications BS and a minimum of 10 years ...

SoC Design and Verification

Hillsboro, OR ยท On-site

$148K - $180K/yr

At least 7 years of experience in RTL Design verification of SoCs (VHDL, Verilog, System Verilog ... Ability to Manage and conduct training for the team. * Worked with companies and seen at least a ...

Director, Design Verification - Samsung Semiconductor TheDRAM Development Lab (DDL) within Samsung ... Plan and manage resources across multiple concurrent projects. * Define and enhance development ...

Perform full-chip SoC integration, including IP integration, clock/reset domain management, power-aware design, and system-level verification to ensure functional correctness and tape-out readiness.

Perform full-chip SoC integration, including IP integration, clock/reset domain management, power-aware design, and system-level verification to ensure functional correctness and tape-out readiness.

SoC Design Engineer

Santa Clara, CA ยท On-site

$156K - $160K/yr

Perform full-chip SoC integration, including IP integration, clock/reset domain management, power-aware design, and system-level verification to ensure functional correctness and tape-out readiness.

Responsible for digital design and verification of image sensor and SoC systems, including IP design, integration, analysis, and validation. Design and verify image sensor control and processing ...

SoC Design and Verification

Hillsboro, OR

$148K - $180K/yr

At least 7 years of experience in RTL Design verification of SoCs (VHDL, Verilog, System verilog ... Ability to Manage and conduct training for the team * Worked with companies and seen at least a ...

Design Verification Engineer

Sunnyvale, CA ยท On-site

$159K - $194K/yr

Your job responsibilities as a Design Verification Engineer will help the team to verify the ... and SoC level. You will help on UVM Testbench development, directed/constrained random test ...

GSoC Design Verification Engineer

San Diego, CA ยท On-site

$144K - $176K/yr

As part of the Global SoC organization, our ASIC Design Verification Engineers bring deep expertise ... Create directed and constrained-random test scenarios to validate functionality and architectural ...

Showing results 41-60

Soc Design Verification Manager Director information

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$37K

$135.8K

$243K

How much do soc design verification manager director jobs pay per year?

As of Sep 13, 2026, the average yearly pay for soc design verification manager director in the United States is $135,763.00, according to ZipRecruiter salary data. Most workers in this role earn between $109,500.00 and $163,000.00 per year, depending on experience, location, and employer.

What does a SoC Design Verification Manager Director do?

A SoC (System on Chip) Design Verification Manager Director oversees teams responsible for ensuring that complex integrated circuits function as intended before manufacturing. They lead the development and execution of verification strategies, manage schedules and resources, and collaborate closely with design, architecture, and validation teams. Their role is critical in identifying and resolving design flaws early in the product development process, thereby improving quality and reducing costly errors. Additionally, they mentor verification engineers and help shape verification methodologies to keep pace with evolving technology.

What are some common challenges faced by a SoC Design Verification Manager Director, and how can they be addressed?

One of the most common challenges for an SoC Design Verification Manager Director is balancing the need for thorough verification coverage with tight project deadlines. Coordinating large, cross-functional teams and integrating verification activities across multiple IP blocks adds complexity. Effective communication, robust planning, and leveraging automation tools can help streamline processes and ensure high-quality outcomes. Encouraging a culture of continuous improvement and fostering collaboration between design and verification teams are also key to overcoming these challenges.

What are the key skills and qualifications needed to thrive as a SoC Design Verification Manager Director, and why are they important?

To thrive as a SoC Design Verification Manager Director, you need deep expertise in digital design, verification methodologies (such as UVM or SystemVerilog), and a strong background in electrical or computer engineering, often with an advanced degree. Familiarity with industry-standard EDA tools (like Cadence, Synopsys, or Mentor Graphics) and experience leading verification teams are typically required. Outstanding leadership, strategic planning, and communication skills help in coordinating large teams and cross-functional projects. These capabilities are crucial for delivering complex SoC products on schedule and ensuring their reliability and performance in competitive markets.

What are popular job titles related to Soc Design Verification Manager Director jobs?

For Soc Design Verification Manager Director jobs, the most frequently searched job titles are:

Sr. Engineer, SoC Design Verification Engineer, System Management Controller

Santa Clara, CA โ€ข On-site

$100K - $500K/yr

Other

Posted 10 days ago


Job description

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

Tenstorrent is seeking a SoC Design Verification Engineer to validate the System Management Controller (SMC) and enable seamless multi-chip integration. In this role, you will design and execute tests, build infrastructure, and debug issues across chiplet-based SoCs. Youโ€™ll have the opportunity to work with remote mentorship while contributing to the foundation of scalable multi-die systems.

This role ishybrid, based out of Toronto, Ontario, Boston, MA or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are
  • Proficient in SystemVerilog, SV-UVM, Python, and C/C++ with strong verification skills.
  • Experienced in writing test plans, building infrastructure, and debugging hardware/software flows.
  • Comfortable working with remote mentorship and distributed teams.
  • Familiar with AI-assisted tools like Copilot, Cursor, and Claude to accelerate verification.
What We Need
  • Develop and maintain SMC tests and supporting DV infrastructure.
  • Write, execute, and track test plans for chiplet and multi-chip SoC designs.
  • Use C/C++ to develop tests compiled, loaded, and executed directly on the DUT.
  • Triage, analyze, and debug issues in close collaboration with design and architecture teams.
What You Will Learn
  • Build deep expertise in system management and multi-die SoC verification.
  • Gain hands-on exposure to advanced interconnect standards like UCIe and BoW.
  • Explore co-simulation methodologies including Cocotb.
  • Learn how AI tools can accelerate test generation, infrastructure, and debug workflows.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

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