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Soc Design Verification Manager Jobs (NOW HIRING)

Qualcomm

SOC Design Verification Engineer-Staff

San Diego, CA · On-site

$144K - $176K/yr

... design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC ... architecture, product management, program management teams) to develop and execute an ...

Qualcomm

SOC Design Verification Engineer-Staff

San Diego, CA · On-site

$144K - $176K/yr

... design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC ... architecture, product management, program management teams) to develop and execute an ...

Apple

Wireless SOC Verification Engineer

Irvine, CA

$122K - $214K/yr

As a Design Verification Engineer on our team, you'll be at the center of the verification effort ... Power Management and Low-Power schemes, DMA, DDR, PCIe, Memory Controller Subsystems, USB, PLL ...

Apple

Wireless SOC Verification Engineer

Irvine, CA

$122K - $214K/yr

As a Design Verification Engineer on our team, you'll be at the center of the verification effort ... Power Management and Low-Power schemes, DMA, DDR, PCIe, Memory Controller Subsystems, USB, PLL ...

Apple

Wireless SOC Verification Engineer

Irvine, CA

$122K - $214K/yr

As a Design Verification Engineer on our team, you'll be at the center of the verification effort ... Power Management and Low-Power schemes, DMA, DDR, PCIe, Memory Controller Subsystems, USB, PLL ...

Apple

Wireless SOC Verification Engineer

Irvine, CA · On-site

$146K - $178K/yr

As part of the Wireless SOC team, you will have the opportunity to verify complex SOCs. Our team ... As a Design Verification Engineer on our team, you'll be at the center of the verification effort ...

Sivaltech

Design Verification Engineer

San Diego, CA · On-site

$144K - $176K/yr

Design Verification Engineer Location: Bay Area, CA (Onsite/Hybrid) Experience: 8+ Years Job ... Develop and execute comprehensive verification plans for ASIC/SoC designs. * Build reusable UVM ...

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Soc Design Verification Manager information

See salary details

$42K

$114.5K

$201.5K

How much do soc design verification manager jobs pay per year?

As of Sep 10, 2026, the average yearly pay for soc design verification manager in the United States is $114,491.00, according to ZipRecruiter salary data. Most workers in this role earn between $83,500.00 and $144,000.00 per year, depending on experience, location, and employer.

What does a SoC Design Verification Manager do?

A SoC (System on Chip) Design Verification Manager oversees the verification process for complex integrated circuits, ensuring that the chip design functions as intended before manufacturing. This role involves leading a team of engineers, defining verification strategies, managing schedules, and coordinating with design and architecture teams. The manager is responsible for planning and executing verification methodologies such as simulation, emulation, and formal verification. They also ensure that all design requirements and quality standards are met, and play a key role in risk management and problem resolution throughout the verification lifecycle.

What are the key skills and qualifications needed to thrive as a SoC Design Verification Manager?

To thrive as a SoC Design Verification Manager, you need deep expertise in digital design, verification methodologies (such as UVM or SystemVerilog), and a relevant engineering degree. Proficiency with industry-standard EDA tools (like Synopsys, Cadence, or Mentor Graphics), scripting languages, and often project management certifications is vital. Strong leadership, communication, and problem-solving skills help you manage teams and coordinate across multiple disciplines. These capabilities are crucial for ensuring high-quality, timely delivery of complex SoC projects in a competitive semiconductor environment.

What are some common challenges faced by a SoC Design Verification Manager when leading verification teams?

As an SoC Design Verification Manager, you may encounter challenges such as coordinating verification efforts across multiple IP blocks, managing shifting project timelines, and ensuring thorough test coverage within tight deadlines. Balancing resource allocation while adapting to evolving design specifications is common, requiring strong communication and organizational skills. Additionally, fostering collaboration between verification engineers, design teams, and software teams is crucial to identify and resolve issues early, ensuring high-quality silicon delivery.

What is the difference between Soc Design Verification Manager vs Soc Design Engineer?

AspectSoc Design Verification ManagerSoc Design Engineer
Primary FocusOversees verification processes, manages teams, ensures verification coverageDesigns and develops SoC components, implements verification tests
Required SkillsVerification methodologies, team leadership, project managementHardware description languages, verification tools, circuit design
Work EnvironmentManagement, coordination, high-level planningHands-on design, coding, testing
CertificationsOften requires verification-related certifications, relevant degreesEngineering degrees, hardware verification certifications

The Soc Design Verification Manager primarily oversees verification teams and processes, focusing on project management and verification coverage. In contrast, the Soc Design Engineer is involved in the hands-on design and implementation of SoC components. Both roles require strong technical skills and relevant certifications, but their responsibilities differ in scope and focus.

What are popular job titles related to Soc Design Verification Manager jobs?

For Soc Design Verification Manager jobs, the most frequently searched job titles are:

Infographic showing various Soc Design Verification Manager job openings in the United States as of September 2026, with employment types broken down into 100% Full Time. Highlights an 100% In-person job distribution, with an average salary of $114,491 per year, or $55 per hour.

ASIC/SoC Design Verification Engineer

Fremont, CA

TetraMem INC
Computer and Peripheral Equipment Manufacturing • 11 - 50 employees
Learn more about TetraMem INCexternal

Full-time

Medical, Retirement, PTO

Re-posted 27 days ago

Job description

Company Description

TetraMem is a fast-growing well-funded startup company working on the next generation of computing platforms with unique ReRAM-based in-memory computing technologies. We are hiring in multiple positions from software to hardware.

We offer a very competitive compensation, commensurate with experience, and a full benefits package including medical, professional PTO, 401k, and other perks.

Job Description

  • Collaborate with design engineers and architects to define, document and implement detailed test plans for the SoC design verification.

  • Build and maintain infrastructure/environment for automation verification of SoC architecture, function and performance.

  • Develop reusable testbench, constrained-random/directed testcases, and verification associated behavioral module for both of block levels and system levels.

  • Develop regression strategy, methodology and tools(scripts). Define and measure the function coverage. Close verification holes for design releases and tape-out.

  • Work with design engineers to debug and identify root causes of simulation failure.

  • Support test engineers for post-silicon validation.

  • Mentor and coach team members and junior engineers. Drive verification efficiency.

Qualifications

  • MS with 8+ years of relevant experience or PhD (with 3+ years of experience) in Electrical Engineering, Computer Engineering, Computer Science or related degree.

  • In depth knowledge of UVM/OVM, Semiformal Verification, assertion-based verification as well as hardware and software co-verification methodology.

  • Extensive experience of building verification infrastructure, test planning, coverage closure, testbench and testcases development for function/performance verification.

  • Proficient experience with Verilog, System Verilog, Python/Perl/TCL/Shell scripting, C/C++, System C and industry mainstream ISAs assembly coding.

  • Familiarity with MIPI, AMBA (APB/AHB/AXI) bus protocol, RISC-V/ARM or DSP core.

  • Experience in verifying designs at both of RTL level and post-P&R gate level.

  • Ability to work in a startup environment, and to work both independently and as a team player with the ability to provide technical leadership to other members of the engineering team

Experience in one or more of the following areas considered a strong plus:

  • Working knowledge of AI/ML Computing, GPU, ISP architectures and accelerators

  • Experience in verifying mix-signal design and interface of digital and analog.

  • Experience of design verification for high speed IO such as PCIE and DDR.

Additional Information

All your information will be kept confidential according to EEO guidelines.

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