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Soc Design Verification Manager Jobs (NOW HIRING)

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Design Verification Manager

Sunnyvale, CA · On-site

$161K - $197K/yr

Design Verification Manager Who We Are: Hewlett Packard Enterprise is the global edge-to-cloud ... Define global verification strategies, infrastructure, and execution plans for complex SoC and IP ...

Qualcomm

SOC Design Verification Engineer

San Diego, CA · On-site

$144K - $176K/yr

... Design Verification Engineers to join our Data Center SoC Verification team. In this role, you will ... Security, RAS, and power-management features * Support emulation and acceleration-based ...

Weekday AI

ASIC/SoC Design & Verification Engineer

$70 - $100/hr

We are seeking experienced ASIC and SoC Design & Verification Engineers to contribute their expertise in digital design, RTL development, functional verification, and silicon implementation to ...

Qualcomm

SOC Design Verification Engineer

San Diego, CA · On-site

$98K - $147K/yr

As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance ...

Qualcomm

SOC Design Verification Engineer

San Diego, CA · On-site

$98K - $147K/yr

As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance ...

Qualcomm

SOC Design Verification Engineer

San Diego, CA · On-site

$98K - $147K/yr

As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance ...

Qualcomm

SOC Design Verification Engineer

San Diego, CA · On-site

$98K - $147K/yr

As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance ...

Qualcomm

SOC Design Verification Engineer

San Diego, CA · On-site

$98K - $147K/yr

As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance ...

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Soc Design Verification Manager information

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$42K

$114.5K

$201.5K

How much do soc design verification manager jobs pay per year?

As of Sep 10, 2026, the average yearly pay for soc design verification manager in the United States is $114,491.00, according to ZipRecruiter salary data. Most workers in this role earn between $83,500.00 and $144,000.00 per year, depending on experience, location, and employer.

What does a SoC Design Verification Manager do?

A SoC (System on Chip) Design Verification Manager oversees the verification process for complex integrated circuits, ensuring that the chip design functions as intended before manufacturing. This role involves leading a team of engineers, defining verification strategies, managing schedules, and coordinating with design and architecture teams. The manager is responsible for planning and executing verification methodologies such as simulation, emulation, and formal verification. They also ensure that all design requirements and quality standards are met, and play a key role in risk management and problem resolution throughout the verification lifecycle.

What are the key skills and qualifications needed to thrive as a SoC Design Verification Manager?

To thrive as a SoC Design Verification Manager, you need deep expertise in digital design, verification methodologies (such as UVM or SystemVerilog), and a relevant engineering degree. Proficiency with industry-standard EDA tools (like Synopsys, Cadence, or Mentor Graphics), scripting languages, and often project management certifications is vital. Strong leadership, communication, and problem-solving skills help you manage teams and coordinate across multiple disciplines. These capabilities are crucial for ensuring high-quality, timely delivery of complex SoC projects in a competitive semiconductor environment.

What are some common challenges faced by a SoC Design Verification Manager when leading verification teams?

As an SoC Design Verification Manager, you may encounter challenges such as coordinating verification efforts across multiple IP blocks, managing shifting project timelines, and ensuring thorough test coverage within tight deadlines. Balancing resource allocation while adapting to evolving design specifications is common, requiring strong communication and organizational skills. Additionally, fostering collaboration between verification engineers, design teams, and software teams is crucial to identify and resolve issues early, ensuring high-quality silicon delivery.

What is the difference between Soc Design Verification Manager vs Soc Design Engineer?

AspectSoc Design Verification ManagerSoc Design Engineer
Primary FocusOversees verification processes, manages teams, ensures verification coverageDesigns and develops SoC components, implements verification tests
Required SkillsVerification methodologies, team leadership, project managementHardware description languages, verification tools, circuit design
Work EnvironmentManagement, coordination, high-level planningHands-on design, coding, testing
CertificationsOften requires verification-related certifications, relevant degreesEngineering degrees, hardware verification certifications

The Soc Design Verification Manager primarily oversees verification teams and processes, focusing on project management and verification coverage. In contrast, the Soc Design Engineer is involved in the hands-on design and implementation of SoC components. Both roles require strong technical skills and relevant certifications, but their responsibilities differ in scope and focus.

What are popular job titles related to Soc Design Verification Manager jobs?

For Soc Design Verification Manager jobs, the most frequently searched job titles are:

Infographic showing various Soc Design Verification Manager job openings in the United States as of September 2026, with employment types broken down into 100% Full Time. Highlights an 100% In-person job distribution, with an average salary of $114,491 per year, or $55 per hour.

SoC Design Verification Engineer

San Jose, CA • On-site

E-Solutions, Inc.
See more jobs at E-Solutions, Inc.external

$159K - $194K/yr

Other

Posted 20 days ago

Job description

Position Title: SoC Design Verification Engineer

Location: San Jose, CA

Remote/Onsite: Onsite

Types of Hire: Fulltime

Job Description: -

We are looking for a highly skilled SoC/Performance DV engineer to drive system-level validation and performance characterization of complex SoCs. The role involves working closely with architecture, design, and software teams to ensure silicon meets performance, power, and functionality targets.

 

Key Responsibilities:

 

  • Develop and execute SoC-level validation and performance verification strategy
  • Build system-level testbenches, workloads, and performance models
  • Analyze performance bottlenecks across CPU, memory, interconnect, and accelerators
  • Perform power and performance trade-off analysis
  • Collaborate with architecture, RTL, and software teams
  • Debug issues at system level (HW + FW/SW interaction)

 

Required Skills:

              Strong experience in SoC-level DV / Performance validation

  • Understanding of CPU architecture, memory hierarchy, NoC/interconnect
  • Expertise in SystemVerilog/UVM + C/C++/Python
  • Experience with performance profiling tools
  • Strong debugging and analytical skills

 Good to Have:

 

Experience in post-silicon validation / bring-up

Knowledge of AI/ML or high-performance computing workloads

Disclaimer: E-Solutions Inc. provides equal employment opportunities (EEO) to all employees and applicants for employment without regard  to race, color, religion, gender, sexual orientation, gender identity or expression, national origin, age, disability, genetic information, marital status, amnesty, or status as a covered veteran in accordance with applicable federal, state and local laws. We especially invite women, minorities, veterans, and individuals with disabilities to apply. EEO/AA/M/F/Vet/Disability.”


SoC Design Verification Engineer1Python,UVM,Verilog,SOC,Design Verification,CPUN/AFull TImeUnited States

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