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Serdes Architect Jobs (NOW HIRING)

Apple

SerDes Micro Architect

Beaverton, OR · On-site

Analog Mixed-Signal (AMS) Team is seeking a self-motivated SERDES Micro Architect to drive the definition of our next generation IPs. The SERDES IPs will be used in Apple silicon offering ...

Apple

SerDes Micro Architect

San Diego, CA · On-site

Analog Mixed-Signal (AMS) Team is seeking a self-motivated SERDES Micro Architect to drive the definition of our next generation IPs. The SERDES IPs will be used in Apple silicon offering ...

Apple

SerDes Micro Architect

Beaverton, OR

Analog Mixed-Signal (AMS) Team is seeking a self-motivated SERDES Micro Architect to drive the definition of our next generation IPs. The SERDES IPs will be used in Apple silicon offering ...

Apple

SerDes Micro Architect

Cupertino, CA · On-site

Analog Mixed-Signal (AMS) Team is seeking a self-motivated SERDES Micro Architect to drive the definition of our next generation IPs. The SERDES IPs will be used in Apple silicon offering ...

191 Altera Corporation

Clocking Architect

San Jose, CA · On-site

$187K - $270K/yr

Develop protocol‑specific clocking solutions for PCIe, high‑speed memory interfaces (DDR5, LPDDR5, HBM), ARM subsystems, configuration interfaces, Ethernet, and SerDes. * Architect clocking for ...

Apple Inc.

SerDes Micro Architect

Beaverton, OR · On-site

Analog Mixed-Signal (AMS) Team is seeking a self‑motivated SERDES Micro Architect to drive the definition of our next generation IPs. The SERDES IPs will be used in Apple silicon offering ...

Apple

SerDes Micro Architect

Cupertino, CA · On-site

$184K - $324K/yr

Analog Mixed-Signal (AMS) Team is seeking a self-motivated SERDES Micro Architect to drive the definition of our next generation IPs. The SERDES IPs will be used in Apple silicon offering ...

Apple

SerDes Micro Architect

San Diego, CA

$175K - $308K/yr

Analog Mixed-Signal (AMS) Team is seeking a self-motivated SERDES Micro Architect to drive the definition of our next generation IPs. The SERDES IPs will be used in Apple silicon offering ...

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Serdes Architect information

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$46.5K

$128.8K

$201.5K

How much do serdes architect jobs pay per year?

As of Sep 14, 2026, the average yearly pay for serdes architect in the United States is $128,756.00, according to ZipRecruiter salary data. Most workers in this role earn between $91,000.00 and $166,000.00 per year, depending on experience, location, and employer.

What is a Serdes Architect?

A Serdes Architect is an engineering professional specializing in the design and development of serializer/deserializer (SerDes) circuits, which are critical for high-speed data transmission in electronics. They create architectures that enable efficient, high-bandwidth communication between chips or system components, often working on complex challenges such as signal integrity, power efficiency, and noise reduction. Serdes Architects collaborate with cross-functional teams to ensure their designs meet performance and reliability standards in industries like telecommunications, data centers, and consumer electronics.

What are the key skills and qualifications needed to thrive as a Serdes Architect?

To thrive as a Serdes Architect, you need deep expertise in high-speed analog and digital circuit design, signal integrity, and experience with relevant engineering degrees (typically in Electrical Engineering). Familiarity with EDA tools such as Cadence, Mentor Graphics, and simulation software, along with knowledge of industry standards like PCIe, USB, or Ethernet, is crucial. Exceptional problem-solving, communication, and collaboration skills help in effectively working with cross-functional teams and translating complex requirements into robust designs. These skills and qualities ensure the delivery of reliable, high-performance Serdes solutions that meet rigorous technical and market demands.

What are some typical challenges faced by Serdes Architects when working on high-speed data transmission projects?

Serdes Architects often encounter challenges related to signal integrity, power consumption, and achieving high data rates while maintaining low error rates. They must carefully design and simulate circuits to minimize jitter, crosstalk, and electromagnetic interference, especially as data rates increase. Collaboration with PCB designers, verification engineers, and system architects is essential to ensure successful integration and optimal performance within the larger system. Staying current with evolving industry standards and leveraging advanced EDA tools are also important to address these challenges effectively.

What cities are hiring for Serdes Architect jobs?

Cities with the most Serdes Architect job openings:

What are popular job titles related to Serdes Architect jobs?

For Serdes Architect jobs, the most frequently searched job titles are:

Infographic showing various Serdes Architect job openings in the United States as of September 2026, with employment types broken down into 100% Full Time. Highlights an 100% In-person job distribution, with an average salary of $128,756 per year, or $61.9 per hour.

Senior Serdes System Design Engineer/Architect

San Jose, CA • On-site

Broadcom
Semiconductor and Electronic Component Manufacturing • 10K+ employees
Learn more about Broadcomexternal

Full-time

Medical, Dental, Vision, Retirement, PTO

Re-posted 6 days ago

Broadcom rating

8.7

Company rating: 8.7 out of 10

Based on 23 frontline employees who took The Breakroom Quiz

Job description

Please Note:

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Job Description:

This is a DSP/Systems Design Engineering position for high-speed Serdes products in the Physical Layer Products (PLP) Division. You will join a team of expert communication system/mixed-signal ASIC designers involved in the design, verification, and implementation of advanced signal processing algorithms for the physical layer of high-speed Serdes at speeds of 100G+.
The types of algorithms that will be implemented include PAM & other higher-order modulation, single/multi-input adaptive equalizers/cancellers, single/multi-dimensioned FEC, digital filters, and interface/integration with analog functions and analysis and compensation for analog circuit non-idealities.
You will be collaborating closely with analog & digital designers to successfully implement the algorithms in advanced silicon technology nodes and work with DVT/lab engineers to validate your designs for high-volume production.
You will support the group contribute to the development of next-generation wireline communications standards at standard bodies such as IEEE and OIF.

Responsibilities include:

  • Develop channel models and run simulations to help define Serdes architecture

  • Define and document signal processing block requirements, architecture, and lab test plan

  • Develop bit-exact MATLAB and C/C++ system models for simulation and verification

  • Develop and run system-level simulation suites of the Serdes to evaluate architectural tradeoffs

  • Work with the design team to perform vector matching verification with RTL simulations

  • Develop, test, and debug firmware associated with physical layer functionality

  • Lab testing and debug of Serdes

  • Documentation/application note development and customer support

  • Support marketing group with customer meetings and collateral

Job Requirements

  • B.S.E.E. plus 8+ years relevant experience OR M.S.E.E. plus 6 years required

  • Expert knowledge in Communication Theory

  • Expert knowledge in Digital Signal Processing algorithms

  • Working knowledge of Analog circuit behavior

  • Working knowledge of Transmission line theory and s-parameter

  • Expert in MATLAB, C/C++ programming

  • Good hands-on skills in the lab

  • Experience in designing high-speed Clock and Data Recovery (CDR) PLLs is a very big plus.

  • Experience in equalization techniques for wireline communication applications such as read-channel is also a very big plus.

  • RTL coding is a plus

  • Knowledge of IEEE 802.3/OIF 100G/200G/400G Serdes standards and PCIe Gen6/Gen7 standards is a plus


Compensation and Benefits


The annual base salary range for this position is USD 121,900.00 To USD 195,000.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.


Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.


Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.


If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

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