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Principal Serdes Engineer Jobs (NOW HIRING)

Intel

Principal SerDes Architect

Folsom, CA · On-site

$220K - $311K/yr

The Role and Impact As a Principal Engineer in Analog Circuit Design, you will be at the forefront ... SerDes fundamentals - Familiarity with UCIe and PCIe specifications - Strong understanding of ...

Intel

Principal SerDes Architect

Santa Clara, CA · On-site

$220K - $311K/yr

The Role and Impact As a Principal Engineer in Analog Circuit Design, you will be at the forefront ... SerDes fundamentals - Familiarity with UCIe and PCIe specifications - Strong understanding of ...

Intel

Principal SerDes Architect

Phoenix, AZ · On-site

$220K - $311K/yr

The Role and Impact As a Principal Engineer in Analog Circuit Design, you will be at the forefront ... SerDes fundamentals - Familiarity with UCIe and PCIe specifications - Strong understanding of ...

Intel

Principal SerDes Architect

Hillsboro, OR · On-site

$220K - $311K/yr

The Role and Impact As a Principal Engineer in Analog Circuit Design, you will be at the forefront ... SerDes fundamentals - Familiarity with UCIe and PCIe specifications - Strong understanding of ...

AIT Global, Inc.

Principal / Lead Engineer

San Jose, CA · On-site

Principal / Lead Engineer Location: San Jose, CA Job Summary: * We are seeking a highly experienced ... The candidate will lead PCIe Controller, PHY and SerDes integration activities, * contribute to ...

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Principal Serdes Engineer information

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How much do principal serdes engineer jobs pay per year?

As of Sep 11, 2026, the average yearly pay for principal serdes engineer in the United States is $147,220.00, according to ZipRecruiter salary data. Most workers in this role earn between $118,500.00 and $173,000.00 per year, depending on experience, location, and employer.

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Infographic showing various Principal Serdes Engineer job openings in the United States as of September 2026, with employment types broken down into 1% Internship, 87% Full Time, 9% Part Time, and 3% Contract. Highlights an 86% Physical, 4% Hybrid, and 10% Remote job distribution, with an average salary of $147,220 per year, or $70.8 per hour.

Principal SerDes Design Engineer

San Jose, CA

Celero Communications, Inc.
See more jobs at Celero Communications, Inc.external

$200K - $300K/yr

Full-time

Re-posted 17 days ago

Job description

Principal SerDes Design Engineer
About the job
We are looking for a SerDes Lead Designer, who is seeking an amazing opportunity delivering disruptive High Speed Interconnect Technology to power next generation AI. Candidate will have the opportunity to architect and design SerDes for next generation transceivers.
What You Will Do
• Define architecture, specifications, and circuit topologies for next-generation SerDes  
• Overview development of system-level modelling, with behavioral models (e.g., MATLAB, SystemVerilog, Verilog-A) to analyze link budgets, equalization strategies and jitter budgeting 
• Design high-performance analog/mixed-signal circuits in advanced node technologies  
• Develop and overview the design of critical blocks including RX/TX equalization (CTLE, DFE), High-speed PLLs, Phase interpolators, DLLs, TDCs 
• Implement digitally assisted analog circuits, background calibration, and adaptive loops to improve Power, Performance, Area 
• Oversee physical layout to minimize parasitics, device stress, electromigration and process variation impacts 
• Overview of the analysis of Signal Integrity and Power Integrity to achieve system-defined targets  
• Lead lab validation, debugging and characterization of SerDes IPs within our state-of-the-art lab 
• Correlate silicon measurements with simulated data, and lead performance optimization in the system environment
What You Will Bring
• Master’s degree and/or PhD in Electrical Engineering or related fields with 10+ years of relevant experience in SerDes design 
• Proven record of taking high-speed SerDes design to tape-out and volume production 
• Experience in lab bring-up, characterization, and debugging designs that reach out production  
• Must have extensive experience with advanced node technologies (16nm/12nm, 7nm, 5nm, 3nm, 2nm processes)  
• Prior experience in cross-functional interaction to deliver IP and ensuring seamless integration in SOCs 
• Strong communication and documentation skills 
Annual Base Salary Range: $200,000 - $300,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.)