Senior Principal Engineer, Systems Design/Architecture Engineering About the Role: The ADI ... Expertise in SERDES, RF CMOS, PLL, or data converter design. * Experience with FinFET or fine-line ...
Senior Principal Engineer, Systems Design/Architecture Engineering About the Role: The ADI ... Expertise in SERDES, RF CMOS, PLL, or data converter design. * Experience with FinFET or fine-line ...
Senior Principal Engineer, Systems Design/Architecture Engineering About the Role: The ADI ... Expertise in SERDES, RF CMOS, PLL, or data converter design. * Experience with FinFET or fine-line ...
Senior Principal Engineer, Systems Design/Architecture Engineering About the Role: The ADI ... Expertise in SERDES, RF CMOS, PLL, or data converter design. * Experience with FinFET or fine-line ...
Principal SI/PI Engineer - 18231
Boxborough, MA · On-site
$165K - $247K/yr
General Information Job Title Principal SI/PI Engineer - 18231 Job ID 18231 City Boxborough State ... Own and execute SI signoff methodology for SerDes channels, including test chip package/board SIPI ...
Principal SI/PI Engineer - 18231
Boxborough, MA · On-site
$165K - $247K/yr
General Information Job Title Principal SI/PI Engineer - 18231 Job ID 18231 City Boxborough State ... Own and execute SI signoff methodology for SerDes channels, including test chip package/board SIPI ...
Principal Engineer, Hardware Design - Networking Date: Aug 27, 2026 Location: Remote Employee US ... High-speed SerDes * Optical and electrical interconnects * Scale-out network fabrics * Network ...
Principal Engineer, Hardware Design - Networking Date: Aug 27, 2026 Location: Remote Employee US ... High-speed SerDes * Optical and electrical interconnects * Scale-out network fabrics * Network ...
Senior Principal Engineer, Systems Design/Architecture Engineering About the Role: The ADI ... Expertise in SERDES, RF CMOS, PLL, or data converter design. * Experience with FinFET or fine-line ...
Senior Principal Engineer, Systems Design/Architecture Engineering About the Role: The ADI ... Expertise in SERDES, RF CMOS, PLL, or data converter design. * Experience with FinFET or fine-line ...
Senior Principal Engineer, Systems Design/Architecture Engineering About the Role: The ADI ... Expertise in SERDES, RF CMOS, PLL, or data converter design. * Experience with FinFET or fine-line ...
Senior Principal Engineer, Systems Design/Architecture Engineering About the Role: The ADI ... Expertise in SERDES, RF CMOS, PLL, or data converter design. * Experience with FinFET or fine-line ...
Responsibilities: * Experienced HSIP product Principal Applications Engineer * Background in ... Strong working knowledge of high-speed (10Gbps+) phy and SerDes * Experience with Ethernet system ...
Responsibilities: * Experienced HSIP product Principal Applications Engineer * Background in ... Strong working knowledge of high-speed (10Gbps+) phy and SerDes * Experience with Ethernet system ...
Principal Analog IC Design Engineer, High Speed SerDes
San Jose, CA · On-site
$136K - $253K/yr
The Principal Analog IC Designer is responsible for the design and development of analog/mixed ... SerDes Circuit Blocks * Driver * Receiver * Serializer * Deserializer * Phase Interpolator * Low ...
Principal Analog IC Design Engineer, High Speed SerDes
San Jose, CA · On-site
$136K - $253K/yr
The Principal Analog IC Designer is responsible for the design and development of analog/mixed ... SerDes Circuit Blocks * Driver * Receiver * Serializer * Deserializer * Phase Interpolator * Low ...
Principal Engineer, Mixed Signal Design Engineering
Dallas, TX · On-site
$185K - $250K/yr
Principal Engineer, Mixed Signal Design Engineering Job Requisition: 1010.629 / R264847 Job ... Transistor-level design, simulation, and verification of high-performance SerDes circuits ...
Principal Engineer, Mixed Signal Design Engineering
Dallas, TX · On-site
$185K - $250K/yr
Principal Engineer, Mixed Signal Design Engineering Job Requisition: 1010.629 / R264847 Job ... Transistor-level design, simulation, and verification of high-performance SerDes circuits ...
Verification Lead / Principal Verification Engineer - PCIe Gen5/Gen6 Location: San Jose, CA ... PIPE, PHY/SerDes, assertions, coverage closure, emulation, and protocol compliance
Verification Lead / Principal Verification Engineer - PCIe Gen5/Gen6 Location: San Jose, CA ... PIPE, PHY/SerDes, assertions, coverage closure, emulation, and protocol compliance
Principal Engineer, Mixed Signal Design Engineering
Dallas, TX · On-site
$185K - $250K/yr
Principal Engineer, Mixed Signal Design Engineering Job Requisition: 1010.629 / R264847 Job ... Transistor-level design, simulation, and verification of high-performance SerDes circuits ...
Principal Engineer, Mixed Signal Design Engineering
Dallas, TX · On-site
$185K - $250K/yr
Principal Engineer, Mixed Signal Design Engineering Job Requisition: 1010.629 / R264847 Job ... Transistor-level design, simulation, and verification of high-performance SerDes circuits ...
## Principal Engineer, Digital IC Design and ArchitectureApplylocations: US, OR, Beaverton: US, CO ... Architect and design digital blocks and subsystems of complex high-speed SerDes ICs, including ...
## Principal Engineer, Digital IC Design and ArchitectureApplylocations: US, OR, Beaverton: US, CO ... Architect and design digital blocks and subsystems of complex high-speed SerDes ICs, including ...
Working from SerDes standards to block specifications, you quickly identify potential circuit ... You are an accomplished analog design engineer with a passion for pushing the boundaries of high ...
Working from SerDes standards to block specifications, you quickly identify potential circuit ... You are an accomplished analog design engineer with a passion for pushing the boundaries of high ...
Senior Principal Engineer -Hardware Signal Integrity & Power Integrity
Santa Clara, CA · Hybrid
$199K - $266K/yr
Senior Principal Engineer, Hardware Application Engineering -- Signal Integrity & Power Integrity ... SerDes Tuning: Provide tuning guidance to customers using simulation data, lab measurements, and ...
Quick apply
Senior Principal Engineer -Hardware Signal Integrity & Power Integrity
Santa Clara, CA · Hybrid
$199K - $266K/yr
Senior Principal Engineer, Hardware Application Engineering -- Signal Integrity & Power Integrity ... SerDes Tuning: Provide tuning guidance to customers using simulation data, lab measurements, and ...
Principal Signal and Power Integrity Engineer
San Jose, CA · On-site
$237K - $250K/yr
At Astera Labs, we seek motivated Principal Signal and Power Integrity Engineers to work on our ... High-speed SERDES channel simulation, and equalization * PI simulations with Ansys/Cadence toolsets
Principal Signal and Power Integrity Engineer
San Jose, CA · On-site
$237K - $250K/yr
At Astera Labs, we seek motivated Principal Signal and Power Integrity Engineers to work on our ... High-speed SERDES channel simulation, and equalization * PI simulations with Ansys/Cadence toolsets
## Principal Engineer, System ArchitectureApplylocations: US, CO, Colorado Springs, Centennialtime ... Develop in-depth understanding of future automotive SerDes market requirements.* Perform ...
## Principal Engineer, System ArchitectureApplylocations: US, CO, Colorado Springs, Centennialtime ... Develop in-depth understanding of future automotive SerDes market requirements.* Perform ...
Position Overview The Principal Hardware Design Engineer will work in Raytheon's Receiver/Exciter ... Experience with high‑speed digital interfaces (JESD204B, DDR3, DDR4, SERDES, 10Gbps Ethernet ...
Position Overview The Principal Hardware Design Engineer will work in Raytheon's Receiver/Exciter ... Experience with high‑speed digital interfaces (JESD204B, DDR3, DDR4, SERDES, 10Gbps Ethernet ...
Remote Employee US Summary Celestica is seeking a Principal Hardware Systems Architect for ... High-speed SerDes * Optical and electrical interconnects * Scale-out network fabrics * Network ...
Remote Employee US Summary Celestica is seeking a Principal Hardware Systems Architect for ... High-speed SerDes * Optical and electrical interconnects * Scale-out network fabrics * Network ...
Principal Product Engineer
San Jose, CA · On-site
We are seeking an experienced and hands-on Principal Product Engineer to lead and develop next ... Hands-on knowledge of NRZ/PAM4 SerDes protocols like PCIe (Gen3 and above), Ethernet (25G and above ...
Principal Product Engineer
San Jose, CA · On-site
We are seeking an experienced and hands-on Principal Product Engineer to lead and develop next ... Hands-on knowledge of NRZ/PAM4 SerDes protocols like PCIe (Gen3 and above), Ethernet (25G and above ...
Sr. Principal Engineer, SoC Architect
San Jose, CA · On-site
$250K - $304K/yr
Position: Sr. Principal Engineer, SoC Architect Location: San Jose, CA Job Id: 585 # of Openings: 0 ... Lead architecture and integration of high-speed interfaces including PCIe, Ethernet, USB, SerDes ...
Sr. Principal Engineer, SoC Architect
San Jose, CA · On-site
$250K - $304K/yr
Position: Sr. Principal Engineer, SoC Architect Location: San Jose, CA Job Id: 585 # of Openings: 0 ... Lead architecture and integration of high-speed interfaces including PCIe, Ethernet, USB, SerDes ...
Principal Serdes Engineer information
See salary details
$74K - $86.6K
3% of jobs
$86.6K - $99.2K
9% of jobs
$99.2K - $111.8K
9% of jobs
$118.1K is the 25th percentile. Wages below this are outliers.
$111.8K - $124.4K
10% of jobs
$124.4K - $137K
10% of jobs
The median wage is $146.6K / yr.
$137K - $149.5K
14% of jobs
$149.5K - $162.1K
13% of jobs
$169.8K is the 75th percentile. Wages above this are outliers.
$162.1K - $174.7K
15% of jobs
$174.7K - $187.3K
11% of jobs
$187.3K - $199.9K
5% of jobs
$199.9K - $212.5K
3% of jobs
$74K
$147.2K
$212.5K
How much do principal serdes engineer jobs pay per year?
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For Principal Serdes Engineer jobs, the most frequently searched job titles are:

Senior Principal Engineer, Systems Design/Architecture Engineering
Somerset, NJ • On-site
Full-time
Medical, Dental, Vision, Retirement, PTO
This job post has expired today. Applications are no longer accepted.
Analog Devices rating
8.7
Based on 19 frontline employees who took The Breakroom Quiz
Job description
About Analog Devices
Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.comand on LinkedIn and X.
Senior Principal Engineer, Systems Design/Architecture Engineering
About the Role:
The ADI Industrial Architecture Team is seeking an experienced Senior Principal Engineer, Systems Design/Architecture Engineering with mixed signal and RF CMOS IC design and architecture experience. The candidate will be a key member of an advanced architecture team and drive an industry-leading high-performance Industrial portfolio into new and more highly integrated market segments. The candidate will have the opportunity to develop system level designs incorporating high-performance and high-frequency RF, data converter, SERDES, DSP and PLL subsystems. A demonstrated track record of driving industry-leading performance and innovation, as manifested through patents, peer-reviewed publications and/or industry-leading product leadership and definition, is required. The ideal candidate is a self-motivated individual and with strong technical, analytical and communication skills. The role will involve significant collaboration with customers, partners and internal centers-of-excellence.
Key Responsibilities:
- Lead the definition and architecture of multi-GHz digital communication products for test and instrumentation systems, establishing signal chain requirements, subsystem partitioning, signal processing, key interfaces, performance/power targets and process nodes.
- Lead detailed analysis for RF, converter, clocking and synchronization sub-systems, digital features, and calibrations/algorithms driven by application requirements. Establish, document, and maintain clear and traceable product and system specifications to the silicon development team and to our customers through collaborative means such as Jama.
- Lead the development of behavioral system modeling infrastructure for mixed-mode simulation and quantitative architecture analysis of IPE devices.
- Lead architecture for clock synthesis and distribution for IPE devices.
- Lead architecture reviews for strategic customer and market opportunities, ensuring proposed solutions are technically credible, differentiated, manufacturable, and aligned with ADI's portfolio strategy and customer use-cases. Communicate architecture alternatives, trade-offs, recommendations, and risks to engineering teams and senior leadership.
- Engage with key customers, ecosystem partners, and standards groups to identify market trends, customer requirements and system economics, and translate those insights into system architectures, product requirements, and technology-roadmap recommendations.
- Partner with the marketing, applications and FAE teams to identify customer pain-points, competitive threats, adoption barriers, and product ease-of-use. Synthesize findings into actionable HW or SW requirements for current and future products.
- Identify and lead greenfield market opportunities, translating emerging customer needs and mega-technology trends into differentiated products and platforms. Create and capture value for ADI through first-mover advantages versus competition leveraging ADI's diverse technologies and IP.
- Identify cross-business-unit product planning for solutions that require multiple ADI technologies where heterogeneous integration and advanced packaging are key to product differentiation.
- Coach (and manage) system architects to strengthen the capabilities and the expansion of the system engineering team in various geographies.
Qualifications:
- BSEE required, MSEE preferred.
- 20+ years of experience in system applications engineering system design/architecture engineering, and design engineering of high-performance RF and mixed-signal IC products and systems.
- Expertise in SERDES, RF CMOS, PLL, or data converter design.
- Experience with FinFET or fine-line planar analog CMOS process technologies and tradeoffs.
- Proficiency in software-defined CMOS communications or radar system design.
- Knowledge of digitally-assisted high-speed analog design.
- Excellent presentation and writing/communication skills.
Preferred Skills:
- Leadership experience in broadband communications subsystem projects.
- Strong understanding of multi-GHz digital communications.
- Proven track record in defining and architecting high-performance communications products incorporating RF ADCs, DACs, PLLs and SERDES.
- Experience in specifying data converters for wideband digital communication systems.
- Ability to manage multi-channel synchronization and crosstalk effectively.
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For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position - except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) - may have to go through an export licensing review process.
Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.
EEO is the Law: Notice of Applicant Rights Under the Law.
Job Req Type: ExperiencedRequired Travel: Yes, 10% of the timeShift Type: 1st Shift/DaysThe expected wage range for a new hire into this position is $184,030 to $266,485.Actual wage offered may vary depending on work location, experience, education, training, external market data, internal pay equity, or other bona fide factors.
This position qualifies for a discretionary performance-based bonus which is based on personal and company factors.
This position includes medical, vision and dental coverage, 401k, paid vacation, holidays, and sick time, and other benefits.
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About Analog Devices
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Analog Devices (NASDAQ: ADI) designs and manufactures semiconductor products and solutions. We enable our customers to interpret the world around us by intelligently bridging the physical and digital worlds with unmatched technologies that sense, measure and connect.
Industry
Electrical equipment, appliance, and component manufacturing
Company size
5,001 - 10,000 Employees
Headquarters location
Norwood, MA, US