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Senior Design Verification Engineer Jobs in Chicago, IL

MaximaTek

Design Verification Engineer

Chicago, IL · On-site

$140K - $171K/yr

Design Verification Engineer We are seeking a detail-oriented Design Verification Engineer to manage and oversee the daily operations of our ASIC/SoC verification workflows and testbench architecture.

suncast

Senior Design Engineer

Batavia, IL · On-site

Creates and verifies designs using CAE, manual methods, and functional test to minimize risk ... The Senior Design Engineer will need a understanding of manufacturing processes from injection ...

Suncast Corporation

Senior Design Engineer

Batavia, IL · On-site

$85 - $115/hr

Creates and verifies designs using CAE, manual methods, and functional test to minimize risk ... The Senior Design Engineer will need a understanding of manufacturing processes from injection ...

suncast

Senior Design Engineer

Batavia, IL · On-site

Creates and verifies designs using CAE, manual methods, and functional test to minimize risk ... The Senior Design Engineer will need a understanding of manufacturing processes from injection ...

Suncast

Senior Design Engineer

Batavia, IL · On-site

Creates and verifies designs using CAE, manual methods, and functional test to minimize risk ... The Senior Design Engineer will need a understanding of manufacturing processes from injection ...

Enpro Industries

Sr. Design Engineer

Harwood Heights, IL · On-site

$119K - $178K/yr

Job Summary A Sr. Design Engineer is responsible for the design, development, and continuous ... design verification using advanced finite element analysis tools. • Develop and implement test ...

Enpro

Sr. Design Engineer

Harwood Heights, IL · On-site

$119K - $178K/yr

Job Summary A Sr. Design Engineer is responsible for the design, development, and continuous ... · Conduct design verification using advanced finite element analysis tools. · Develop and ...

Sterling Engineering Inc.

SR Design Engineer

Wheaton, IL · On-site +1

$135K - $160K/yr

Senior Design Engineer - Electric Distribution Location: Remote/Wheaton, IL Hire Type: Direct Hire Salary: $135K-$160K/YR Benefits: Medical, Dental, Vision, Life Insurance, 401(k) with company match ...

Intellihot Inc

SR DESIGN ENGINEER

Vernon Hills, IL · On-site

$110 - $130/hr

Position SummaryThe Sr Design Engineer will work in a cross-functional that designs, develops, manufactures, and services Intellihot tankless water heaters, boilers, and other products. Knowledge of ...

New

The Will Group

Senior Design Engineer

Wheaton, IL · On-site

$130K - $165K/yr

The Will Group is seeking a Senior Design Engineer - Electrical Distribution to help lead utility engineering projects serving Commonwealth Edison and other Exelon operating companies. This is an ...

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All JobsDesign Verification Engineer JobsSenior Design Verification Engineer JobsSenior Design Verification Engineer Jobs in Chicago, IL

Senior Design Verification Engineer information

See Chicago, IL salary details

$65K

$125.2K

$197.4K

How much do senior design verification engineer jobs pay per year?

As of Sep 4, 2026, the average yearly pay for senior design verification engineer in Chicago, IL is $125,226.00, according to ZipRecruiter salary data. Most workers in this role earn between $97,900.00 and $142,800.00 per year, depending on experience, location, and employer.

What is a senior design verification engineer?

Senior Design Verification Engineers are experienced professionals responsible for ensuring that hardware designs, such as integrated circuits or system-on-chip (SoC) components, meet all functional specifications and quality standards before manufacturing. They create and execute verification plans, develop testbenches, and use simulation tools to identify and resolve design issues. Their expertise helps prevent costly errors, ensuring reliable and functional products. Typically, they collaborate closely with design, validation, and product engineering teams and often mentor junior engineers.

What are the key skills and qualifications needed to thrive as a senior design verification engineer?

A Senior Design Verification Engineer requires deep expertise in digital design principles, verification methodologies (such as UVM or OVM), and a degree in electrical or computer engineering. Familiarity with hardware description languages (like Verilog or VHDL), simulation tools (e.g., Synopsys VCS, Cadence Incisive), and scripting languages (such as Python or TCL) is typically expected. Exceptional problem-solving, attention to detail, and strong communication skills help in collaborating with cross-functional teams and navigating complex verification challenges. These skills and qualifications are vital to ensure robust, high-quality hardware designs that meet performance and reliability standards.

What are some typical challenges faced by senior design verification engineers when working on complex chip designs?

Senior Design Verification Engineers often encounter challenges such as managing verification of increasingly complex and large-scale integrated circuits, ensuring comprehensive coverage, and identifying hard-to-find corner-case bugs. They frequently collaborate across cross-functional teams, including design, firmware, and test engineering, to clarify specifications and resolve issues. Effective communication and a proactive approach to debugging and process improvement are critical, as is keeping up with evolving verification methodologies and tools to ensure high-quality, on-time project delivery.

What is the difference between Senior Design Verification Engineer vs Design Verification Engineer?

AspectSenior Design Verification EngineerDesign Verification Engineer
Required CredentialsBachelor's or Master's in Electrical Engineering, Computer Engineering, or related field; experience in verification tools and methodologiesBachelor's degree in Electrical Engineering, Computer Engineering, or related field; entry-level experience in verification
Work EnvironmentDesign teams, hardware/software verification labs, collaborative projectsVerification teams, testing labs, development environments
Employer & Industry UsageSemiconductor, electronics, hardware development companiesSimilar industries, often as entry or mid-level roles within verification teams

The main difference is experience level and responsibility. Senior Design Verification Engineers typically lead verification efforts, mentor junior staff, and handle complex verification tasks, while Design Verification Engineers focus on executing verification plans and testing designs under supervision. Both roles require similar technical skills and industry knowledge, but the senior role involves more leadership and strategic planning.

What are the most commonly searched types of Design Verification Engineer jobs in Chicago, IL?

The most popular types of Design Verification Engineer jobs in Chicago, IL are:

What are popular job titles related to Senior Design Verification Engineer jobs in Chicago, IL?

For Senior Design Verification Engineer jobs in Chicago, IL, the most frequently searched job titles are:

What job categories do people searching Senior Design Verification Engineer jobs in Chicago, IL look for?

The top searched job categories for Senior Design Verification Engineer jobs in Chicago, IL are:

What cities near Chicago, IL are hiring for Senior Design Verification Engineer jobs?

Cities near Chicago, IL with the most Senior Design Verification Engineer job openings:

Senior Design Verification Engineer jobs near you
Infographic showing various Senior Design Verification Engineer job openings in Chicago, IL as of August 2026, with employment types broken down into 87% Full Time, 9% Part Time, and 4% Contract. Highlights an 84% Physical, 5% Hybrid, and 11% Remote job distribution, with an average salary of $125,226 per year, or $60.2 per hour.

Design Verification Engineer

MaximaTek

Chicago, IL • On-site

$140K - $171K/yr

Other

Posted 4 days ago

Job description

About the Role: Design Verification Engineer

We are seeking a detail-oriented Design Verification Engineer to manage and oversee the daily operations of our ASIC/SoC verification workflows and testbench architecture. In this role, you will act as the vital link between our RTL design teams, system architects, and EDA tool vendors, ensuring that all hardware designs are verified with maximum efficiency, scalability, and adherence to strict functional coverage standards and industry security specifications.


Core Responsibilities

Verification Lifecycle Management: Coordinate daily verification activities, including test plan development, testbench architecture creation, constrained random stimulus generation, and regression scheduling. Regulatory & Functional Compliance: Maintain comprehensive verification documentation and version control; ensure all design activities align with industry security standards, safety frameworks (e.g., ISO 26262), and company SOPs. Data & Signal Integrity: Perform accurate assertion-based verification (SVA) and functional coverage analysis; ensure rigorous verification metrics are applied to simulation logs and hardware specifications. Risk Mitigation: Monitor coverage gaps, bug trends, and simulation performance bottlenecks; report significant design bugs or verification non-compliance promptly to management and stakeholders.

Quality Assurance: Author and maintain test plan specifications; assist in internal and external audits to ensure quality standards and tape-out readiness criteria for complex digital systems are met. Technical Liaison: Serve as the primary point of contact for EDA tool providers and third-party IP vendors during performance reviews and technical audits.


Qualifications

Education: Bachelor’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field (Required). Experience: 0–5 years of experience in digital design verification, ASIC/SoC development, or hardware research environments. Technical Skills (Required): Strong understanding of Digital Logic Design, Computer Architecture, and Verification Methodologies (UVM/OVM). Proficiency in hardware description and verification languages (SystemVerilog, Verilog, VHDL) and scripting languages (Python, Perl, Tcl). Familiarity with EDA simulation tools (e.g., Synopsys VCS, Cadence Xcelium, Siemens Questa) and regression management pipelines. Excellent technical writing and organizational skills. Preferred Skills: Experience with Formal Verification tools or Emulation platforms (e.g., Palladium, Zebu). Knowledge of high-speed protocols (PCIe, Ethernet, USB) or bus architectures (AMBA AXI/AHB). Knowledge of low-power verification (UPF/CPF) and mixed-signal simulation. What We Offer

Targeted Placement: Direct marketing to our network of hiring managers in the Tech, Semiconductor, Manufacturing, and MedTech industries. Technical Resume Rebuild: Optimization of your profile to highlight verification expertise alongside silicon debug efficiency. Interview Coaching: Guidance on technical coding interviews, SystemVerilog/UVM concepts, and hardware verification system design case studies.


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Email your updated resume to: manavi@maximatek.com

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