Rtl Verification Engineer Jobs (NOW HIRING)

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About Altera

At Altera, our independence as the world's largest pureplay FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industryleading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely-empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.

About the Role

We are seeking a highly experienced Design Verification Engineer to join Altera's Design Verification organization. In this critical role, you will be responsible for verifying the correctness, performance, and compliance of FPGA and SoC designs, with a strong focus on PCIe subsystems. You will partner closely with RTL designers, architects, and firmware engineers to develop and execute comprehensive verification strategies for next-generation programmable devices.

This is a senior individual contributor role requiring deep domain expertise in functional verification methodologies, PCIe protocol compliance, and advanced simulation and formal techniques. You will have significant influence over verification architecture decisions and be expected to mentor junior engineers on best practices.

Responsibilities

• Develop, implement, and maintain comprehensive UVM-based testbenches for PCIe IP, subsystems, and full-chip FPGA/SoC designs.

• Define and own the verification plan for assigned design blocks, covering functional coverage, code coverage, assertions, and protocol compliance checks.

• Author and review SystemVerilog assertions (SVA) and functional coverage models to ensure complete specification coverage.

• Develop directed and constrained-random test scenarios targeting PCIe Gen4/Gen5/Gen6 transactions, error injection, TLP/DLLP handling, and link training sequences.

• Integrate and validate third-party PCIe VIP models and co-simulate with firmware and software stacks to verify end-to-end behavior.

• Analyze simulation regressions, triaging and root-causing failures across RTL, testbench, and environment components.

• Perform formal property verification (FPV) and equivalence checking to complement simulation-based verification efforts.

• Collaborate with hardware architects and RTL designers to review design specifications and provide early DV feedback on testability and design-for-verification.

• Drive closure of verification milestones, including feature, coverage, and sign-off criteria, across multiple concurrent FPGA and SoC programs.

• Mentor and provide technical guidance to junior and mid-level design verification engineers.

• Contribute to the development of reusable verification IP, components, and infrastructure to improve team productivity across programs.

• Participate in design reviews, verification reviews, and cross-functional technical discussions with architecture, RTL, and physical design teams.

Salary Range

The pay range below is for Bay Area California only. Actual salary may vary based ona number offactors including job location, job-related knowledge, skills, experiences,trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.

$142.6K- $206.5KUSD

We use artificial intelligence to screen, assess, or select applicants for the position.Applicants must be eligible for any required U.S. export authorizations.

Qualifications:

Minimum Qualifications

• Bachelor's Degree in Electrical Engineering, Computer Engineering, or a closely related technical discipline, plus a minimum of 8+ years of professional Design Verification experience in the semiconductor or FPGA industry.

• Minimum of 4+ years of hands-on experience verifying PCIe IP or subsystems, including at least 1 generation of PCIe Gen4 or later (Gen5/Gen6 strongly preferred).

• Minimum of 7+ ears of experience writing SystemVerilog and UVM-based testbenches, including sequence libraries, scoreboards, functional coverage groups, and assertion-based verification.

• Minimum of 4+ years of experience developing constrained-random test environments for complex SoC or FPGA designs, with demonstrated closure of coverage metrics exceeding 95%.

Preferred Qualifications

• Master's or Ph.D. in Electrical Engineering, Computer Engineering, or a related field.

• Experience verifying PCIe Gen5 or Gen6 designs, including CXL (Compute Express Link) 2.0/3.0 protocol layers built on PCIe physical and transaction layers.

• Familiarity with FPGA architecture, including high-speed transceivers, hard IP blocks, and embedded processor subsystems (e.g., Intel Agilex, Stratix, Arria product families).

Job Type: RegularShift:Shift 1 (United States of America)Primary Location:San Jose, California, United StatesAdditional Locations:Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.