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Remote Work From Home Dft Engineer Jobs (NOW HIRING)

Purple Hires Inc

DFT Engineer

Plano, TX · Remote

Remote, (Onsite) Duration: Contract Year of Exp: 8+ yrs to 15 yrs. We are seeking a highly ... Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration. * Review RTL, synthesis, LEC ...

Purple Hires Inc

ASIC DFT Engineer

Plano, TX · Remote

Remote, (Onsite) Duration: Contract Year of Exp: 8+ yrs to 15 yrs. We are seeking a highly ... Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration. * Review RTL, synthesis, LEC ...

Tenstorrent

DFT Engineer

Santa Clara, CA · On-site +1

$100K - $500K/yr

You will work with Tenstorrent worldwide experts and leaders in the USA, Japan and other countries ... This role is remote based out of the United States. We welcome candidates at various experience ...

Purple Hires Inc

Lead ASIC DFT Engineer

San Jose, CA · Remote

Title - Lead ASIC DFT Engineer Location - Remote (must be aligned with PST time zone) Below is the ... Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration. * Review RTL, synthesis, LEC ...

EnCharge AI

Lead DFT Engineer

$200K - $250K/yr

Lead DFT Engineer Developing silicon for edge-to-cloud computing isn't just about speed; it's about balancing high-performance data processing with extreme power efficiency and reliability in remote ...

Online Remote Jobs

Data Entry - Remote work from home

$17.50 - $23.25/hr

About the job Data Entry - Remote work from home Remote work from home. data entry clerk, typing, copy pest, survey answer, survey complete, Sign Up, get started now. Thank you for checking us out!

EnCharge AI

Lead DFT Engineer

$200K - $250K/yr

Lead DFT Engineer Developing silicon for edge-to-cloud computing isn't just about speed; it's about balancing high-performance data processing with extreme power efficiency and reliability in remote ...

AO Globe Life

Remote Work From Home Representative

Dallas, TX · On-site +1

$15.75 - $21.50/hr

Remote Work From Home Representative 100% Remote | Entry-Level Friendly | Full Training Provided | Flexible Schedule Looking for a remote opportunity where you can learn, grow, and build a long-term ...

Purple Hires Inc

Lead ASIC DFT Engineer

Plano, TX · Remote

... Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for ... Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration. * Review RTL, synthesis, LEC ...

K2 Space

Senior DFT Engineer

$170K - $250K/yr

Backed by over $1 billion in total funding from leading investors including Altimeter Capital ... The Role We are seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead and ...

Online Remote Jobs

Data Entry - 100% Remote Work From Home

$17.50 - $23.25/hr

About the job Data Entry - 100% Remote Work From Home NOTE: Only US citizens will apply. Applications from other countries are not acceptable. Don't waste your / my precious time unnecessarily by ...

State Farm

Telemarketer-Remote Work From Home

Greenfield, IN · On-site +1

$80K - $100K/yr

From day one you will begin paid training in a remote work environment. * All equipment will be given to you. * Must be living in the US * Work at home (W@H) requirements which include a professional ...

Sapsol Technologies Inc

Lead ASIC DFT Engineer

We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and ... Strong communication skills and the ability to work independently with minimal ramp-up.

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$44K

$106.4K

$173.5K

How much do remote work from home dft engineer jobs pay per year?

As of Aug 28, 2026, the average yearly pay for remote work from home dft engineer in the United States is $106,386.00, according to ZipRecruiter salary data. Most workers in this role earn between $76,000.00 and $132,500.00 per year, depending on experience, location, and employer.

What is a remote work from home DFT engineer?

A Remote Work From Home DFT (Design for Test) Engineer is a professional who specializes in designing and implementing testability features in integrated circuits (ICs) to ensure their quality and functionality. Working remotely, they use specialized tools and techniques to add test structures to semiconductor designs, allowing for efficient testing during manufacturing. Their responsibilities include developing test plans, analyzing design coverage, collaborating with design and verification teams, and troubleshooting issues found during testing. This role requires strong expertise in digital design, test methodologies, and the use of EDA tools, all of which can be performed effectively from a home office with the right setup.

What are the key skills and qualifications needed to thrive as a remote work from home DFT engineer?

To thrive as a Remote Work From Home DFT (Design for Test) Engineer, you need a solid background in digital design, test methodologies, and a degree in electrical engineering or a related field. Familiarity with EDA tools such as Synopsys DFT tools, Mentor Tessent, and scripting languages like Python or TCL is essential, along with knowledge of scan insertion, ATPG, and fault simulation. Excellent problem-solving abilities, self-motivation, and effective virtual communication are key soft skills for collaborating across distributed teams. These skills ensure robust testability of designs, seamless coordination in remote environments, and successful delivery of high-quality silicon products.

How do remote work from home DFT engineers typically collaborate with hardware and verification teams given the distributed work environment?

Remote Work From Home DFT (Design for Test) Engineers often rely on a combination of video conferencing, collaborative design tools, and shared repositories to work closely with hardware and verification teams. Effective communication is crucial, as tasks such as testbench development, scan insertion, and ATPG require alignment with both design and verification schedules. Regular virtual meetings and clear documentation help maintain project momentum and ensure seamless integration of DFT features into the overall design. Additionally, many companies provide secure VPN access and utilize project management platforms to coordinate tasks and track progress.

What is the difference between Remote Work From Home Dft Engineer vs Remote Work From Home Test Engineer?

AspectRemote Work From Home Dft EngineerRemote Work From Home Test Engineer
CredentialsBachelor's in Electrical/Computer Engineering, DFT certificationBachelor's in Computer Science/Engineering, testing certifications
Work EnvironmentDesigning and implementing DFT strategies remotelyDeveloping and executing testing plans remotely
Industry UsageSemiconductor, electronics manufacturingSoftware, hardware development

Both roles often require similar technical credentials and are performed in remote settings. DFT Engineers focus on designing testability features for hardware, while Test Engineers concentrate on validating product functionality. The choice depends on whether your expertise is in hardware design or software testing, but both roles are integral in tech industries and commonly offer remote work options.

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Remote Work From Home Dft Engineer jobs near you
Infographic showing various Remote Work From Home Dft Engineer job openings in the United States as of August 2026, with employment types broken down into 71% Full Time, 10% Part Time, and 19% Contract. Highlights an 100% Remote job distribution, with an average salary of $106,386 per year, or $51.1 per hour.

DFT Engineer

Plano, TX • Remote

Purple Hires Inc
See more jobs at Purple Hires Incexternal

Contractor

Re-posted just now

Job description

Role: Lead ASIC DFT Engineer
Location: Remote, (Onsite)
Duration: Contract
 
Year of Exp: 8+ yrs to 15 yrs.
 
Job Description:
We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues. The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield.
Key Responsibilities:
  • Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
  • Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high coverage and robust testability.
  • Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up phases.
  • Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon issues.
  • Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis.
  • Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation issues.
  • Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug.
  • Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration.
  • Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality.
  • Act as a technical escalation point for advanced DFT and post-silicon debug issues.
  • Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation.
  • Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and debug productivity.
Required Skills & Qualifications:
  • Strong hands-on experience in ASIC DFT with end-to-end ownership.
  • Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
  • Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
  • Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
  • Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
  • Experience with MBIST implementation and verification; SMS experience preferred.
  • Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
  • Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
  • Proven post-silicon debug and silicon bring-up experience.
  • Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
  • Strong communication skills and the ability to work independently with minimal ramp-up.
Preferred Experience:
  • MBIST post-silicon validation.
  • ATPG simulations and fault coverage debug.
  • DFT RTL, DFD, DFT verification, and IP-level DFT integration.
  • DFT SDC creation and DFT timing closure support.
  • Boundary scan, iJTAG, SSN, and design-for-debug methodologies.
  • TCL/PERL scripting for DFT automation, reporting, and debug.
  • Experience working across multiple ASIC technology nodes and complex product development cycles.
  • Familiarity with yield learning, diagnosis, and manufacturing test optimization.