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Remote Principal Rf Engineer Jobs in Arizona (NOW HIRING)

PowerLattice

Principal Digital Design Engineer

Chandler, AZ · On-site +1

$200K - $250K/yr

About the Role We are seeking a highly skilled and hands-on Principal Digital Design Engineer to ... While we are primarily seeking candidates in HQ-Vancouer and Chandler, remote flexibility may be ...

Insight

$133K - $178K/yr

Partner with cloud architects, DevOps, and development teams to integrate security early * Provide ... Remote

Cognizant

Consulting Principal, AI Architect

Phoenix, AZ · Remote

$122K - $194K/yr

Collaborate with cross‑functional consulting and engineering teams to integrate AI solutions with ... Based on this role's business requirements, this is a remote position open to qualified applicants ...

USAA

Software Engineer I

Phoenix, AZ · On-site +1

USAA roles may offer remote or hybrid flexibility for active-duty military spouses consistent with ... The above description reflects the details considered necessary to describe the principal functions ...

USAA

AI/ML Engineer II

Phoenix, AZ · On-site +1

$113K - $136K/yr

USAA roles may offer remote or hybrid flexibility for active-duty military spouses consistent with ... The above description reflects the details considered necessary to describe the principal functions ...

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Remote Principal Rf Engineer information

What are the key skills and qualifications needed to thrive as a Remote Principal RF Engineer, and why are they important?

To thrive as a Remote Principal RF Engineer, you need deep expertise in RF design, electromagnetic theory, and signal processing, usually backed by a degree in electrical engineering and substantial industry experience. Familiarity with RF simulation tools (like ADS, HFSS, or CST), network analyzers, and relevant certifications (such as FCC or IEEE) is often required. Strong problem-solving abilities, effective communication, and project leadership are standout soft skills in this role. These competencies are essential for delivering high-performance RF solutions, ensuring regulatory compliance, and effectively leading cross-functional engineering teams.

How does a Remote Principal RF Engineer typically collaborate with cross-functional teams while working offsite?

As a Remote Principal RF Engineer, collaboration with cross-functional teams—such as hardware designers, software engineers, and project managers—is usually facilitated through regular virtual meetings, collaborative design platforms, and shared documentation tools. Despite being offsite, you’ll often participate in technical reviews, offer guidance on RF design challenges, and coordinate integration efforts to ensure project milestones are met. Successfully managing clear communication and documentation is essential in this remote environment to keep all team members aligned. Many organizations also use project management software and version control systems to streamline collaboration and ensure transparency across different time zones.

What is a Remote Principal RF Engineer?

A Remote Principal RF Engineer is a senior-level professional who specializes in designing, developing, and optimizing radio frequency (RF) systems and components, such as antennas, transmitters, and receivers, while working remotely. They often lead teams, oversee complex projects, and provide technical guidance to ensure high performance and compliance with industry standards. Their expertise is critical in industries like telecommunications, aerospace, and defense, where reliable wireless communication is essential.

What is the difference between Remote Principal Rf Engineer vs Remote Senior Rf Engineer?

AspectRemote Principal Rf EngineerRemote Senior Rf Engineer
CredentialsAdvanced degrees, certifications in RF engineeringRelevant experience, certifications often preferred
Work EnvironmentLeadership roles, strategic planning, cross-team collaborationHands-on design, testing, troubleshooting
Industry UsageUsed in high-level design and architecture roles in telecom and wireless industriesCommon in development and implementation teams

The Remote Principal Rf Engineer typically holds a leadership position with strategic responsibilities, while the Remote Senior Rf Engineer focuses more on technical expertise and hands-on tasks. Both roles require RF engineering credentials, but the principal level emphasizes project oversight and industry influence.

What are the most commonly searched types of Principal Rf Engineer jobs in Arizona? The most popular types of Principal Rf Engineer jobs in Arizona are:
What are popular job titles related to Remote Principal Rf Engineer jobs in Arizona? For Remote Principal Rf Engineer jobs in Arizona, the most frequently searched job titles are:
What job categories do people searching Remote Principal Rf Engineer jobs in Arizona look for? The top searched job categories for Remote Principal Rf Engineer jobs in Arizona are:
What cities in Arizona are hiring for Remote Principal Rf Engineer jobs? Cities in Arizona with the most Remote Principal Rf Engineer job openings:
Remote Principal Rf Engineer jobs near you

Principal Digital Design Engineer

PowerLattice

Chandler, AZ • On-site, Remote

$200K - $250K/yr

Full-time

Medical, Dental, Vision, Retirement

Re-posted 10 days ago

Job description

Hybrid requiring 3 days a week onsite in the office
Reports To: Head of Engineering
About Us
PowerLattice is a well-funded semiconductor start-up company backed by well-known large Silicon Valley VCs. The company is working on the industry's groundbreaking chiplet solution for a fundamental shift in how high-performance chips get powered, paving the way for the next generation of AI and advanced computing.
About the Role
We are seeking a highly skilled and hands-on Principal Digital Design Engineer to drive the microarchitecture, design, and implementation of complex digital systems and SoC components. This role combines deep technical contribution with team leadership, requiring active involvement from microarchitecture definition through RTL development and into back-end implementation and silicon bring-up.
Key Responsibilities
  • Architecture & Hands-On Design
  • Define microarchitecture for complex digital blocks and subsystems
  • Actively contribute to RTL development for key components
  • Drive design tradeoffs across performance, power, area (PPA), and testability
  • RTL Development & Integration
  • Write, review, and integrate high-quality RTL
  • Lead block- and chip-level integration, resolving interface and system issues
  • Ensure designs are clean for lint, CDC/RDC, and synthesis
  • Back-End & Implementation Ownership
  • Ensure RTL is optimized for synthesis, timing, and physical design
  • Work on scan insertion, test architecture, and coverage closure
  • Perform, review and debug logic equivalence checking (LEC) results between RTL and netlists
  • Define and validate timing constraints (SDC) and complete timing closure
  • Drive and implement timing and functional ECOs as needed
  • Design Quality & Signoff
  • Drive signoff readiness including lint, CDC/RDC, synthesis, LEC, and timing checks
  • Ensure designs meet functional, timing, power, and test requirements
  • Support silicon bring-up, debug, and root-cause analysis
  • Cross-Functional Collaboration
  • Work closely with verification, physical design, DFT, and firmware teams
  • Align design decisions with verification plans and implementation
    Constraints
  • Act as the technical bridge between front-end and back-end teams

Qualifications
This is a Hybrid role requiring 3 days a week onsite at our HQ's in Vancouver, WA (Greater Portland Area) or Chandler, AZ. While we are primarily seeking candidates in HQ-Vancouer and Chandler, remote flexibility may be considered for exceptional candidates in Silicon Valley, CA.
  • Bachelor's or master's degree in electrical engineering, Computer Engineering, or related field
  • 10+ years of experience in digital design with significant hands-on RTL development
  • Proven track record of delivering complex SoC or subsystem designs to tapeout
  • Strong expertise in:
    • RTL design and microarchitecture
    • SoC integration and standard interfaces
  • Hands-on experience with back-end flows, including:
    • Scan insertion and DFT (scan, MBIST, test coverage)
    • Logic equivalence checking (LEC)
    • Static timing analysis (STA) and timing closure
    • Timing constraint development and debug (SDC)
  • Solid understanding of:
    • Clocking, resets, CDC/RDC, and low-power design
    • Synthesis and physical design implications
  • Experience with industry-standard EDA tools (Synopsys, Cadence)
  • Experience with low-power methodologies (UPF/CPF)
  • Strong debugging and problem-solving skills

Preferred Qualifications
  • Familiarity with advanced technology nodes and implementation challenges
  • Experience with formal verification techniques
  • Experience with silicon bring-up and post-silicon debug

Compensation & Benefits
Anticipated annual base salary for Member of Technical Staff: $200,000 - $250,000
  • Stock option grant
  • Comprehensive benefits package including health, dental, vision, and 401(k)

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