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Remote Asic Rtl Design Engineer Jobs in Kearny, NJ

Lakeview Loan Servicing

Design Engineer

Manhattan, NY · Remote

$140K - $180K/yr

Overview The Design Engineer on the Horizon team plays a critical role in shaping the look, feel ... This is a fully remote position that offers a competitive salary range of $140,000 to $180,000 USD ...

Ambrook

Design Engineer

New York, NY · On-site +1

$140K - $210K/yr

Sitting at the center of design and engineering, you work well across disciplines to get things ... Work-from-home/remote office stipend * Wellness stipend * Professional development stipend Our ...

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Remote Asic Rtl Design Engineer information

See Kearny, NJ salary details

$98.3K

$157K

$211.2K

How much do remote asic rtl design engineer jobs pay per year?

As of Jul 13, 2026, the average yearly pay for remote asic rtl design engineer in Kearny, NJ is $157,040.00, according to ZipRecruiter salary data. Most workers in this role earn between $137,500.00 and $188,200.00 per year, depending on experience, location, and employer.

What is a Remote ASIC RTL Design Engineer?

A Remote ASIC RTL Design Engineer is a professional who specializes in designing the Register Transfer Level (RTL) code for Application-Specific Integrated Circuits (ASICs) while working remotely. Their main responsibilities include creating and verifying digital circuit designs using hardware description languages such as Verilog or VHDL. These engineers collaborate with hardware teams to ensure functionality, performance, and power requirements are met, all while operating from a location outside of a traditional office setting. They often use remote collaboration tools and simulation software to review and validate designs before fabrication.

What are the key skills and qualifications needed to thrive as a Remote ASIC RTL Design Engineer, and why are they important?

To thrive as a Remote ASIC RTL Design Engineer, you need a solid background in digital design, computer engineering, and hardware description languages like Verilog or VHDL, often supported by a relevant degree. Proficiency with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics, as well as experience with simulation, synthesis, and version control systems, is crucial. Strong problem-solving, self-motivation, and effective remote communication skills distinguish top performers in this role. These skills ensure accurate, efficient design cycles and effective collaboration across distributed teams, leading to successful chip delivery.

What is the difference between Remote Asic Rtl Design Engineer vs Remote Digital IC Design Engineer?

AspectRemote Asic Rtl Design EngineerRemote Digital IC Design Engineer
Primary FocusRegister Transfer Level (RTL) design for ASICsDigital integrated circuit design at the IC level
Skills & CertificationsHDL (Verilog/VHDL), EDA tools, verificationHDL, circuit simulation, verification, FPGA experience
Work EnvironmentASIC design teams, hardware developmentIC design teams, semiconductor industry
Industry UsageUsed in ASIC development for various applicationsUsed in digital IC manufacturing and prototyping

Both roles involve digital design and HDL skills, but the Remote Asic Rtl Design Engineer focuses on RTL coding for ASICs, while the Remote Digital IC Design Engineer covers broader digital IC design, including FPGA and chip-level work. They share similar credentials and work environments, often overlapping in semiconductor companies.

What are some common challenges faced by Remote ASIC RTL Design Engineers, and how can they be addressed?

Remote ASIC RTL Design Engineers often face challenges such as coordinating with distributed teams across different time zones and ensuring effective communication during complex design phases. To address these issues, it’s important to establish clear documentation practices, utilize collaboration tools like version control and video conferencing, and schedule regular check-ins with team members. Additionally, staying proactive in seeking feedback and clarifying design specifications helps ensure alignment and reduces misunderstandings. Building strong virtual relationships with verification and backend teams can also streamline the handoff process and overall project flow.
What cities near Kearny, NJ are hiring for Remote Asic Rtl Design Engineer jobs? Cities near Kearny, NJ with the most Remote Asic Rtl Design Engineer job openings:
Remote Asic Rtl Design Engineer jobs near you
Design Verification Engineer - Fully Remote | Upto $175/hr

Design Verification Engineer - Fully Remote | Upto $175/hr

Mercor

New York, NY • Remote

$175/hr

Full-time

Re-posted 17 days ago

Job description

About the job

Mercor connects elite creative and technical talent with leading AI research labs. Headquartered in San Francisco, our investors include Benchmark, General Catalyst, Peter Thiel, Adam D'Angelo, Larry Summers, and Jack Dorsey.

Position: RTL Design Engineers
Type: Contract
Compensation: $100–$175/hour
Location: Remote
Duration: 3+ months
Commitment: 40 hours/week

Role Responsibilities

  • Evaluate digital chip design workflows to enhance AI model training and evaluation.
  • Design and verify RTL components using Verilog/SystemVerilog.
  • Collaborate with architecture, verification, and implementation teams to improve model outputs.
  • Develop reusable verification components and testbench infrastructure.
  • Leverage LLM-based tools to accelerate chip design and verification processes.
  • Work independently and asynchronously to meet project deadlines.

Qualifications

Must-Have

  • 3–10 years of experience in digital RTL design or design verification.
  • Strong proficiency in Verilog/SystemVerilog and UVM.
  • Solid understanding of digital design fundamentals: FSMs, datapaths, pipelines, FIFOs, arbiters, clock/reset domains, bus protocols.
  • Experience with ASIC design flows and common EDA tools.
  • Ability to write clear design documentation and communicate technical tradeoffs.

Preferred

  • Knowledge of AMBA protocols (AXI, AHB, APB).
  • Background in CPU, GPU/ML accelerator, networking, memory subsystem, PCIe/high-speed IO, SoC interconnect, low-power design.
  • Exposure to formal verification or SV/UVM-based design verification.

Start Date

  • Week of 04/23; applications reviewed on a rolling basis.

Compensation & Legal

  • Hourly contractor, Paid weekly.

Application Process (Takes 20–30 mins to complete)

  • Upload resume
  • AI interview based on your resume
  • Submit form

Resources & Support

  • For details about the interview process and platform information, please check: https://talent.docs.mercor.com/welcome
  • For any help or support, reach out to: support@mercor.com

PS: Our team reviews applications daily. Please complete your AI interview and application steps to be considered for this opportunity.